ATE516540T1 - Datenvalidierung mittels prozessorbefehlen - Google Patents

Datenvalidierung mittels prozessorbefehlen

Info

Publication number
ATE516540T1
ATE516540T1 AT07758495T AT07758495T ATE516540T1 AT E516540 T1 ATE516540 T1 AT E516540T1 AT 07758495 T AT07758495 T AT 07758495T AT 07758495 T AT07758495 T AT 07758495T AT E516540 T1 ATE516540 T1 AT E516540T1
Authority
AT
Austria
Prior art keywords
operands
buffer
data validation
processor commands
checksum
Prior art date
Application number
AT07758495T
Other languages
English (en)
Inventor
Steven King
Frank Berry
Abhiejeet Joglekar
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE516540T1 publication Critical patent/ATE516540T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Retry When Errors Occur (AREA)
  • Executing Machine-Instructions (AREA)
AT07758495T 2006-03-20 2007-03-14 Datenvalidierung mittels prozessorbefehlen ATE516540T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/384,527 US7925957B2 (en) 2006-03-20 2006-03-20 Validating data using processor instructions
PCT/US2007/063946 WO2007109466A1 (en) 2006-03-20 2007-03-14 Validating data using processor instructions

Publications (1)

Publication Number Publication Date
ATE516540T1 true ATE516540T1 (de) 2011-07-15

Family

ID=38522766

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07758495T ATE516540T1 (de) 2006-03-20 2007-03-14 Datenvalidierung mittels prozessorbefehlen

Country Status (5)

Country Link
US (2) US7925957B2 (de)
EP (1) EP1997006B1 (de)
CN (1) CN101405699B (de)
AT (1) ATE516540T1 (de)
WO (1) WO2007109466A1 (de)

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US8464125B2 (en) * 2009-12-10 2013-06-11 Intel Corporation Instruction-set architecture for programmable cyclic redundancy check (CRC) computations
US9471308B2 (en) 2013-01-23 2016-10-18 International Business Machines Corporation Vector floating point test data class immediate instruction
US9823924B2 (en) 2013-01-23 2017-11-21 International Business Machines Corporation Vector element rotate and insert under mask instruction
US9513906B2 (en) 2013-01-23 2016-12-06 International Business Machines Corporation Vector checksum instruction
US9778932B2 (en) 2013-01-23 2017-10-03 International Business Machines Corporation Vector generate mask instruction
US9804840B2 (en) 2013-01-23 2017-10-31 International Business Machines Corporation Vector Galois Field Multiply Sum and Accumulate instruction
US9715385B2 (en) 2013-01-23 2017-07-25 International Business Machines Corporation Vector exception code
US9154161B1 (en) * 2014-04-01 2015-10-06 Cisco Technology, Inc. Calculating cyclic redundancy checks over overlapping windows of streaming data
US9477562B1 (en) 2015-04-23 2016-10-25 Microsemi Storage Solutions (Us), Inc. Apparatus and method for minimizing exclusive-OR (XOR) computation time
US20230224079A1 (en) * 2022-01-07 2023-07-13 Keysight Technologies, Inc. Methods, systems, and computer readable media for measuring data integrity in time sensitive networks

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Also Published As

Publication number Publication date
US20110145679A1 (en) 2011-06-16
WO2007109466A1 (en) 2007-09-27
US20070226580A1 (en) 2007-09-27
CN101405699A (zh) 2009-04-08
EP1997006A1 (de) 2008-12-03
US7925957B2 (en) 2011-04-12
EP1997006B1 (de) 2011-07-13
US8156401B2 (en) 2012-04-10
EP1997006A4 (de) 2010-06-02
CN101405699B (zh) 2011-11-16

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