IL157828A0 - Semiconductor structure implementing sacrificial material and methods for making and implementing the same - Google Patents

Semiconductor structure implementing sacrificial material and methods for making and implementing the same

Info

Publication number
IL157828A0
IL157828A0 IL15782802A IL15782802A IL157828A0 IL 157828 A0 IL157828 A0 IL 157828A0 IL 15782802 A IL15782802 A IL 15782802A IL 15782802 A IL15782802 A IL 15782802A IL 157828 A0 IL157828 A0 IL 157828A0
Authority
IL
Israel
Prior art keywords
implementing
methods
interconnect metallization
stubs
sacrificial layer
Prior art date
Application number
IL15782802A
Other languages
English (en)
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp filed Critical Lam Res Corp
Publication of IL157828A0 publication Critical patent/IL157828A0/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
    • H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Peptides Or Proteins (AREA)
IL15782802A 2001-03-28 2002-03-26 Semiconductor structure implementing sacrificial material and methods for making and implementing the same IL157828A0 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/821,415 US6984892B2 (en) 2001-03-28 2001-03-28 Semiconductor structure implementing low-K dielectric materials and supporting stubs
PCT/US2002/009617 WO2002103791A2 (en) 2001-03-28 2002-03-26 Semiconductor structure implementing sacrificial material and methods for making and implementing the same

Publications (1)

Publication Number Publication Date
IL157828A0 true IL157828A0 (en) 2004-03-28

Family

ID=25233349

Family Applications (3)

Application Number Title Priority Date Filing Date
IL15782802A IL157828A0 (en) 2001-03-28 2002-03-26 Semiconductor structure implementing sacrificial material and methods for making and implementing the same
IL157828A IL157828A (en) 2001-03-28 2003-09-09 Semiconductor structure implementing sacrificial material
IL201926A IL201926A0 (en) 2001-03-28 2009-11-04 Semiconductor structure implementing sacrificial material and methods for making and implementing the same

Family Applications After (2)

Application Number Title Priority Date Filing Date
IL157828A IL157828A (en) 2001-03-28 2003-09-09 Semiconductor structure implementing sacrificial material
IL201926A IL201926A0 (en) 2001-03-28 2009-11-04 Semiconductor structure implementing sacrificial material and methods for making and implementing the same

Country Status (10)

Country Link
US (3) US6984892B2 (xx)
EP (1) EP1415344B1 (xx)
JP (1) JP4283106B2 (xx)
KR (1) KR100874521B1 (xx)
CN (2) CN100481437C (xx)
AT (1) ATE328366T1 (xx)
DE (1) DE60211915T2 (xx)
IL (3) IL157828A0 (xx)
TW (1) TW533574B (xx)
WO (1) WO2002103791A2 (xx)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1521300A1 (en) * 2003-09-30 2005-04-06 STMicroelectronics S.r.l. Circuit structure integrated on a semiconductor substrate and relevant manufacturing method
US8263983B2 (en) 2003-10-28 2012-09-11 Semiconductor Energy Laboratory Co., Ltd. Wiring substrate and semiconductor device
KR100571391B1 (ko) * 2003-12-23 2006-04-14 동부아남반도체 주식회사 반도체 소자의 금속 배선 구조의 제조 방법
CN1705098A (zh) * 2004-06-02 2005-12-07 中芯国际集成电路制造(上海)有限公司 用于低k中间电介质层的方法及结构
US20060035457A1 (en) * 2004-08-10 2006-02-16 Carter Richard J Interconnection capacitance reduction
JP2006147877A (ja) * 2004-11-19 2006-06-08 Fujitsu Ltd 半導体装置及びその製造方法
JP5180426B2 (ja) * 2005-03-11 2013-04-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5204370B2 (ja) * 2005-03-17 2013-06-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20060216924A1 (en) * 2005-03-28 2006-09-28 Zhen-Cheng Wu BEOL integration scheme for etching damage free ELK
US7071099B1 (en) 2005-05-19 2006-07-04 International Business Machines Corporation Forming of local and global wiring for semiconductor product
US7737020B1 (en) * 2005-12-21 2010-06-15 Xilinx, Inc. Method of fabricating CMOS devices using fluid-based dielectric materials
JP4666308B2 (ja) * 2006-02-24 2011-04-06 富士通セミコンダクター株式会社 半導体装置の製造方法
US7537511B2 (en) * 2006-03-14 2009-05-26 Micron Technology, Inc. Embedded fiber acoustic sensor for CMP process endpoint
CN103560107A (zh) * 2006-10-09 2014-02-05 英闻萨斯有限公司 形成互连结构的方法
TW200826233A (en) * 2006-12-15 2008-06-16 Touch Micro System Tech Method of fabricating metal interconnects and inter-metal dielectric layer thereof
US7608538B2 (en) * 2007-01-05 2009-10-27 International Business Machines Corporation Formation of vertical devices by electroplating
JP5209269B2 (ja) * 2007-10-29 2013-06-12 日本電信電話株式会社 電気装置及びその製造方法
CN101593719B (zh) * 2008-05-26 2010-08-11 中芯国际集成电路制造(北京)有限公司 自支撑空气桥互连结构的制作方法
US8299622B2 (en) 2008-08-05 2012-10-30 International Business Machines Corporation IC having viabar interconnection and related method
JP2011040582A (ja) * 2009-08-11 2011-02-24 Fuji Xerox Co Ltd 発光素子およびその製造方法
CN101834153B (zh) * 2010-04-22 2015-05-20 上海华虹宏力半导体制造有限公司 增强芯片封装时抗压能力的方法及其芯片
US8896120B2 (en) * 2010-04-27 2014-11-25 International Business Machines Corporation Structures and methods for air gap integration
US9293366B2 (en) 2010-04-28 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias with improved connections
US8525354B2 (en) * 2011-10-13 2013-09-03 United Microelectronics Corporation Bond pad structure and fabricating method thereof
US9105634B2 (en) 2012-06-29 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Voids in interconnect structures and methods for forming the same
KR20140089650A (ko) 2013-01-03 2014-07-16 삼성디스플레이 주식회사 액정 표시 장치 및 그 제조 방법
CN103943550B (zh) * 2013-01-18 2016-07-27 中芯国际集成电路制造(上海)有限公司 顶层金属互连层的制造方法
CN105453235B (zh) * 2013-08-30 2018-04-13 日立化成株式会社 浆料、研磨液组、研磨液、基体的研磨方法以及基体
JP6295802B2 (ja) * 2014-04-18 2018-03-20 ソニー株式会社 高周波デバイス用電界効果トランジスタおよびその製造方法、ならびに高周波デバイス
US20150340322A1 (en) * 2014-05-23 2015-11-26 Rf Micro Devices, Inc. Rf switch structure having reduced off-state capacitance
WO2016151684A1 (ja) * 2015-03-20 2016-09-29 株式会社日立国際電気 半導体装置の製造方法、記録媒体及び基板処理装置
US10211052B1 (en) * 2017-09-22 2019-02-19 Lam Research Corporation Systems and methods for fabrication of a redistribution layer to avoid etching of the layer
US11299827B2 (en) 2018-05-17 2022-04-12 James Tolle Nanoconductor smart wearable technology and electronics
US10515905B1 (en) * 2018-06-18 2019-12-24 Raytheon Company Semiconductor device with anti-deflection layers
KR102107345B1 (ko) 2019-12-11 2020-05-06 조성민 코킹 및 궤적연습용 골프 스윙 연습기
CN114088201A (zh) * 2021-03-26 2022-02-25 北京北方高业科技有限公司 基于cmos工艺的红外探测器像元和红外探测器
US20220336365A1 (en) * 2021-04-15 2022-10-20 Samsung Electronics Co., Ltd. Semiconductor devices
US20230240079A1 (en) * 2022-01-27 2023-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of manufacturing semiconductor structure
KR102770644B1 (ko) 2022-08-25 2025-02-21 (주)디엠비에이치 2개의 imu센서를 이용한 스윙연습기
KR20250050308A (ko) 2023-10-06 2025-04-15 (주)디엠비에이치 2개의 imu센서를 이용한 스윙연습기

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63313896A (ja) 1987-06-17 1988-12-21 Nippon Telegr & Teleph Corp <Ntt> エアギャップ多層配線の形成方法
JPH01235254A (ja) * 1988-03-15 1989-09-20 Nec Corp 半導体装置及びその製造方法
JPH02220464A (ja) 1989-02-22 1990-09-03 Toshiba Corp 半導体装置及びその製造方法
US5219791A (en) * 1991-06-07 1993-06-15 Intel Corporation TEOS intermetal dielectric preclean for VIA formation
US5413962A (en) 1994-07-15 1995-05-09 United Microelectronics Corporation Multi-level conductor process in VLSI fabrication utilizing an air bridge
US6057224A (en) 1996-03-29 2000-05-02 Vlsi Technology, Inc. Methods for making semiconductor devices having air dielectric interconnect structures
US5990507A (en) * 1996-07-09 1999-11-23 Kabushiki Kaisha Toshiba Semiconductor device having ferroelectric capacitor structures
JP2962272B2 (ja) * 1997-04-18 1999-10-12 日本電気株式会社 半導体装置の製造方法
US6277728B1 (en) * 1997-06-13 2001-08-21 Micron Technology, Inc. Multilevel interconnect structure with low-k dielectric and method of fabricating the structure
US6184121B1 (en) * 1997-07-10 2001-02-06 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
JP2971454B2 (ja) * 1997-08-21 1999-11-08 松下電子工業株式会社 半導体装置とその製造方法
US6333255B1 (en) * 1997-08-21 2001-12-25 Matsushita Electronics Corporation Method for making semiconductor device containing low carbon film for interconnect structures
US6078088A (en) * 1999-01-05 2000-06-20 Advanced Micro Devices, Inc. Low dielectric semiconductor device with rigid lined interconnection system
US6657302B1 (en) * 1999-01-12 2003-12-02 Agere Systems Inc. Integration of low dielectric material in semiconductor circuit structures
US6204165B1 (en) * 1999-06-24 2001-03-20 International Business Machines Corporation Practical air dielectric interconnections by post-processing standard CMOS wafers
JP2001185552A (ja) * 1999-12-27 2001-07-06 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2001196372A (ja) * 2000-01-13 2001-07-19 Mitsubishi Electric Corp 半導体装置
US6555467B2 (en) * 2001-09-28 2003-04-29 Sharp Laboratories Of America, Inc. Method of making air gaps copper interconnect
US6713835B1 (en) * 2003-05-22 2004-03-30 International Business Machines Corporation Method for manufacturing a multi-level interconnect structure

Also Published As

Publication number Publication date
ATE328366T1 (de) 2006-06-15
CN100481437C (zh) 2009-04-22
US20090004845A1 (en) 2009-01-01
WO2002103791A2 (en) 2002-12-27
KR100874521B1 (ko) 2008-12-16
IL201926A0 (en) 2010-06-16
IL157828A (en) 2010-06-16
CN1531755A (zh) 2004-09-22
CN101488473A (zh) 2009-07-22
WO2002103791A3 (en) 2004-02-19
US7875548B2 (en) 2011-01-25
US6984892B2 (en) 2006-01-10
US20050194688A1 (en) 2005-09-08
CN101488473B (zh) 2011-07-13
KR20030086613A (ko) 2003-11-10
US20060043596A1 (en) 2006-03-02
DE60211915D1 (de) 2006-07-06
JP4283106B2 (ja) 2009-06-24
DE60211915T2 (de) 2007-02-08
JP2005519454A (ja) 2005-06-30
TW533574B (en) 2003-05-21
US7425501B2 (en) 2008-09-16
EP1415344A2 (en) 2004-05-06
EP1415344B1 (en) 2006-05-31

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