IL140566A - A method for preventing bridging between multi-crystalline properties at micro scales - Google Patents

A method for preventing bridging between multi-crystalline properties at micro scales

Info

Publication number
IL140566A
IL140566A IL14056600A IL14056600A IL140566A IL 140566 A IL140566 A IL 140566A IL 14056600 A IL14056600 A IL 14056600A IL 14056600 A IL14056600 A IL 14056600A IL 140566 A IL140566 A IL 140566A
Authority
IL
Israel
Prior art keywords
patterned edge
polycrystalline
average grain
spaced apart
equal
Prior art date
Application number
IL14056600A
Other languages
English (en)
Hebrew (he)
Other versions
IL140566A0 (en
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IL140566A0 publication Critical patent/IL140566A0/xx
Publication of IL140566A publication Critical patent/IL140566A/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24777Edge feature
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24942Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
    • Y10T428/2495Thickness [relative or absolute]
    • Y10T428/24967Absolute thicknesses specified
    • Y10T428/24975No layer or component greater than 5 mils thick

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
IL14056600A 2000-03-14 2000-12-26 A method for preventing bridging between multi-crystalline properties at micro scales IL140566A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/525,095 US6555204B1 (en) 2000-03-14 2000-03-14 Method of preventing bridging between polycrystalline micro-scale features

Publications (2)

Publication Number Publication Date
IL140566A0 IL140566A0 (en) 2002-02-10
IL140566A true IL140566A (en) 2004-06-01

Family

ID=24091891

Family Applications (2)

Application Number Title Priority Date Filing Date
IL14056600A IL140566A (en) 2000-03-14 2000-12-26 A method for preventing bridging between multi-crystalline properties at micro scales
IL14183201A IL141832A0 (en) 2000-03-14 2001-03-05 Method of preventing bridging between polycrystalline micro-scale features

Family Applications After (1)

Application Number Title Priority Date Filing Date
IL14183201A IL141832A0 (en) 2000-03-14 2001-03-05 Method of preventing bridging between polycrystalline micro-scale features

Country Status (11)

Country Link
US (1) US6555204B1 (ko)
EP (1) EP1264341B1 (ko)
JP (1) JP4068845B2 (ko)
KR (1) KR100454783B1 (ko)
CN (1) CN100338755C (ko)
AU (1) AU5218801A (ko)
DE (1) DE60143472D1 (ko)
IL (2) IL140566A (ko)
MY (1) MY124911A (ko)
TW (1) TW517366B (ko)
WO (1) WO2001073841A2 (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3643116B2 (ja) * 2002-06-28 2005-04-27 住友精密工業株式会社 可動電気回路用導電膜および振動式ジャイロ
KR101139630B1 (ko) 2010-12-09 2012-05-30 한양대학교 산학협력단 식별키 생성 장치 및 방법
KR101118826B1 (ko) * 2011-02-15 2012-04-20 한양대학교 산학협력단 물리적 공격을 방어하는 암호화 장치 및 암호화 방법
ES2593302T3 (es) 2011-03-31 2016-12-07 Ictk Co., Ltd. Aparato y método para generar un valor digital
EP2747335B1 (en) 2011-08-16 2017-01-11 ICTK Co., Ltd. Device and method for puf-based inter-device security authentication in machine-to-machine communication
KR102186475B1 (ko) 2013-12-31 2020-12-03 주식회사 아이씨티케이 홀딩스 랜덤한 디지털 값을 생성하는 장치 및 방법
US9184134B2 (en) * 2014-01-23 2015-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device structure
CN113921581A (zh) 2021-07-09 2022-01-11 北京京东方技术开发有限公司 显示面板和显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980752A (en) * 1986-12-29 1990-12-25 Inmos Corporation Transition metal clad interconnect for integrated circuits
JP2811126B2 (ja) 1991-05-02 1998-10-15 三菱電機株式会社 半導体集積回路装置の配線接続構造およびその製造方法
US5441915A (en) * 1992-09-01 1995-08-15 Taiwan Semiconductor Manufacturing Company Ltd. Process of fabrication planarized metallurgy structure for a semiconductor device
DE4232814A1 (de) * 1992-09-30 1994-03-31 Sel Alcatel Ag Metallische Kontaktflächen auf einem Halbleitersubstrat
US5943601A (en) * 1997-04-30 1999-08-24 International Business Machines Corporation Process for fabricating a metallization structure
KR100252846B1 (ko) * 1997-12-26 2000-05-01 김영환 반도체소자의 배선 및 그의 제조방법

Also Published As

Publication number Publication date
CN100338755C (zh) 2007-09-19
IL141832A0 (en) 2002-03-10
TW517366B (en) 2003-01-11
KR20020086609A (ko) 2002-11-18
WO2001073841A3 (en) 2002-03-07
DE60143472D1 (de) 2010-12-30
EP1264341B1 (en) 2010-11-17
MY124911A (en) 2006-07-31
US6555204B1 (en) 2003-04-29
KR100454783B1 (ko) 2004-11-06
JP4068845B2 (ja) 2008-03-26
CN1518764A (zh) 2004-08-04
WO2001073841A2 (en) 2001-10-04
IL140566A0 (en) 2002-02-10
JP2004511082A (ja) 2004-04-08
EP1264341A2 (en) 2002-12-11
AU5218801A (en) 2001-10-08

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KB Patent renewed
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