IL113134A - Mapping of multiple sets of commands - Google Patents

Mapping of multiple sets of commands

Info

Publication number
IL113134A
IL113134A IL113134A IL11313495A IL113134A IL 113134 A IL113134 A IL 113134A IL 113134 A IL113134 A IL 113134A IL 11313495 A IL11313495 A IL 11313495A IL 113134 A IL113134 A IL 113134A
Authority
IL
Israel
Prior art keywords
instruction
bit
bit program
program instruction
words
Prior art date
Application number
IL113134A
Other languages
English (en)
Hebrew (he)
Other versions
IL113134A0 (en
Original Assignee
Advanced Risc Mach Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Mach Ltd filed Critical Advanced Risc Mach Ltd
Publication of IL113134A0 publication Critical patent/IL113134A0/xx
Publication of IL113134A publication Critical patent/IL113134A/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017Runtime instruction translation, e.g. macros
    • G06F9/30174Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30189Instruction operation extension or modification according to execution mode, e.g. mode flag
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30196Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
IL113134A 1994-05-03 1995-03-26 Mapping of multiple sets of commands IL113134A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9408873A GB2289354B (en) 1994-05-03 1994-05-03 Multiple instruction set mapping

Publications (2)

Publication Number Publication Date
IL113134A0 IL113134A0 (en) 1995-06-29
IL113134A true IL113134A (en) 1998-03-10

Family

ID=10754569

Family Applications (1)

Application Number Title Priority Date Filing Date
IL113134A IL113134A (en) 1994-05-03 1995-03-26 Mapping of multiple sets of commands

Country Status (13)

Country Link
US (1) US5568646A (ko)
EP (1) EP0758463B1 (ko)
JP (2) JP3171201B2 (ko)
KR (3) KR100323191B1 (ko)
CN (1) CN1088214C (ko)
DE (1) DE69503046T2 (ko)
GB (1) GB2289354B (ko)
IL (1) IL113134A (ko)
IN (1) IN189950B (ko)
MY (1) MY114381A (ko)
RU (1) RU2137184C1 (ko)
TW (1) TW242678B (ko)
WO (1) WO1995030187A1 (ko)

Families Citing this family (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2290395B (en) 1994-06-10 1997-05-28 Advanced Risc Mach Ltd Interoperability with multiple instruction sets
AU7246496A (en) * 1995-10-06 1997-04-28 Advanced Micro Devices Inc. Instruction decoder including emulation using indirect specifiers
US5926642A (en) 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5794063A (en) * 1996-01-26 1998-08-11 Advanced Micro Devices, Inc. Instruction decoder including emulation using indirect specifiers
GB2308470B (en) * 1995-12-22 2000-02-16 Nokia Mobile Phones Ltd Program memory scheme for processors
US5790824A (en) * 1996-03-18 1998-08-04 Advanced Micro Devices, Inc. Central processing unit including a DSP function preprocessor which scans instruction sequences for DSP functions
US5867681A (en) * 1996-05-23 1999-02-02 Lsi Logic Corporation Microprocessor having register dependent immediate decompression
US5794010A (en) * 1996-06-10 1998-08-11 Lsi Logic Corporation Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor
US5896519A (en) * 1996-06-10 1999-04-20 Lsi Logic Corporation Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions
US6711667B1 (en) * 1996-06-28 2004-03-23 Legerity, Inc. Microprocessor configured to translate instructions from one instruction set to another, and to store the translated instructions
DE19629130A1 (de) * 1996-07-19 1998-05-14 Philips Patentverwaltung Signalprozessor
EP0858168A1 (en) 1997-01-29 1998-08-12 Hewlett-Packard Company Field programmable processor array
EP0858167A1 (en) 1997-01-29 1998-08-12 Hewlett-Packard Company Field programmable processor device
US5925124A (en) * 1997-02-27 1999-07-20 International Business Machines Corporation Dynamic conversion between different instruction codes by recombination of instruction elements
KR100451712B1 (ko) * 1997-03-12 2004-11-16 엘지전자 주식회사 멀티플리케이션장치및방법
US5881258A (en) * 1997-03-31 1999-03-09 Sun Microsystems, Inc. Hardware compatibility circuit for a new processor architecture
US5930491A (en) * 1997-06-18 1999-07-27 International Business Machines Corporation Identification of related instructions resulting from external to internal translation by use of common ID field for each group
JP3781519B2 (ja) * 1997-08-20 2006-05-31 富士通株式会社 プロセッサの命令制御機構
US6438679B1 (en) * 1997-11-03 2002-08-20 Brecis Communications Multiple ISA support by a processor using primitive operations
DE69841256D1 (de) 1997-12-17 2009-12-10 Panasonic Corp Befehlsmaskierung um Befehlsströme einem Prozessor zuzuleiten
DE69827589T2 (de) 1997-12-17 2005-11-03 Elixent Ltd. Konfigurierbare Verarbeitungsanordnung und Verfahren zur Benutzung dieser Anordnung, um eine Zentraleinheit aufzubauen
US6567834B1 (en) 1997-12-17 2003-05-20 Elixent Limited Implementation of multipliers in programmable arrays
US6012138A (en) * 1997-12-19 2000-01-04 Lsi Logic Corporation Dynamically variable length CPU pipeline for efficiently executing two instruction sets
US6044460A (en) * 1998-01-16 2000-03-28 Lsi Logic Corporation System and method for PC-relative address generation in a microprocessor with a pipeline architecture
EP0942357A3 (en) 1998-03-11 2000-03-22 Matsushita Electric Industrial Co., Ltd. Data processor compatible with a plurality of instruction formats
US6079010A (en) * 1998-03-31 2000-06-20 Lucent Technologies Inc. Multiple machine view execution in a computer system
US6189094B1 (en) * 1998-05-27 2001-02-13 Arm Limited Recirculating register file
US7013456B1 (en) 1999-01-28 2006-03-14 Ati International Srl Profiling execution of computer programs
US7941647B2 (en) 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US6954923B1 (en) 1999-01-28 2005-10-11 Ati International Srl Recording classification of instructions executed by a computer
US8065504B2 (en) 1999-01-28 2011-11-22 Ati International Srl Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor
US7111290B1 (en) 1999-01-28 2006-09-19 Ati International Srl Profiling program execution to identify frequently-executed portions and to assist binary translation
US6978462B1 (en) 1999-01-28 2005-12-20 Ati International Srl Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled
US8127121B2 (en) 1999-01-28 2012-02-28 Ati Technologies Ulc Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US7065633B1 (en) 1999-01-28 2006-06-20 Ati International Srl System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
US8074055B1 (en) * 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US7275246B1 (en) 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US6826748B1 (en) 1999-01-28 2004-11-30 Ati International Srl Profiling program execution into registers of a computer
WO2000068782A1 (fr) * 1999-05-06 2000-11-16 Hitachi, Ltd. Procede de mise au point d'un circuit integre a semiconducteur
US6820189B1 (en) * 1999-05-12 2004-11-16 Analog Devices, Inc. Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation
US6779107B1 (en) 1999-05-28 2004-08-17 Ati International Srl Computer execution by opportunistic adaptation
US7254806B1 (en) 1999-08-30 2007-08-07 Ati International Srl Detecting reordered side-effects
JP2001142692A (ja) * 1999-10-01 2001-05-25 Hitachi Ltd 2つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法
US6934832B1 (en) 2000-01-18 2005-08-23 Ati International Srl Exception mechanism for a computer
US7353368B2 (en) * 2000-02-15 2008-04-01 Intel Corporation Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support
US20020004897A1 (en) * 2000-07-05 2002-01-10 Min-Cheng Kao Data processing apparatus for executing multiple instruction sets
US6633969B1 (en) 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
GB2367653B (en) * 2000-10-05 2004-10-20 Advanced Risc Mach Ltd Restarting translated instructions
GB2367651B (en) * 2000-10-05 2004-12-29 Advanced Risc Mach Ltd Hardware instruction translation within a processor pipeline
US7149878B1 (en) 2000-10-30 2006-12-12 Mips Technologies, Inc. Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
US7711926B2 (en) * 2001-04-18 2010-05-04 Mips Technologies, Inc. Mapping system and method for instruction set processing
GB2376100B (en) * 2001-05-31 2005-03-09 Advanced Risc Mach Ltd Data processing using multiple instruction sets
US7107439B2 (en) * 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions
US20070005942A1 (en) * 2002-01-14 2007-01-04 Gil Vinitzky Converting a processor into a compatible virtual multithreaded processor (VMP)
US20060149927A1 (en) * 2002-11-26 2006-07-06 Eran Dagan Processor capable of multi-threaded execution of a plurality of instruction-sets
JP4090908B2 (ja) * 2003-02-21 2008-05-28 シャープ株式会社 画像処理装置および画像形成装置
TWI230899B (en) * 2003-03-10 2005-04-11 Sunplus Technology Co Ltd Processor and method using parity check to proceed command mode switch
GB2402764B (en) 2003-06-13 2006-02-22 Advanced Risc Mach Ltd Instruction encoding within a data processing apparatus having multiple instruction sets
US7707389B2 (en) * 2003-10-31 2010-04-27 Mips Technologies, Inc. Multi-ISA instruction fetch unit for a processor, and applications thereof
GB2414308B (en) * 2004-05-17 2007-08-15 Advanced Risc Mach Ltd Program instruction compression
US20060155974A1 (en) * 2005-01-07 2006-07-13 Moyer William C Data processing system having flexible instruction capability and selection mechanism
US20060174089A1 (en) * 2005-02-01 2006-08-03 International Business Machines Corporation Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture
US7793078B2 (en) * 2005-04-01 2010-09-07 Arm Limited Multiple instruction set data processing system with conditional branch instructions of a first instruction set and a second instruction set sharing a same instruction encoding
US7958335B2 (en) * 2005-08-05 2011-06-07 Arm Limited Multiple instruction set decoding
GB2435116B (en) * 2006-02-10 2010-04-07 Imagination Tech Ltd Selecting between instruction sets in a microprocessors
US7500210B2 (en) * 2006-11-15 2009-03-03 Mplicity Ltd. Chip area optimization for multithreaded designs
US7802252B2 (en) * 2007-01-09 2010-09-21 International Business Machines Corporation Method and apparatus for selecting the architecture level to which a processor appears to conform
US20090044159A1 (en) * 2007-08-08 2009-02-12 Mplicity Ltd. False path handling
EP2203814A4 (en) * 2007-09-19 2012-11-07 Kpit Cummins Infosystems Ltd MECHANISM FOR RELEASING PLUG AND PLAY HARDWARE COMPONENTS FOR SEMI-AUTOMATIC SOFTWARE MIGRATION
US8347067B2 (en) * 2008-01-23 2013-01-01 Arm Limited Instruction pre-decoding of multiple instruction sets
US20100115239A1 (en) * 2008-10-29 2010-05-06 Adapteva Incorporated Variable instruction width digital signal processor
GB2478726B (en) * 2010-03-15 2013-12-25 Advanced Risc Mach Ltd Mapping between registers used by multiple instruction sets
GB2484489A (en) * 2010-10-12 2012-04-18 Advanced Risc Mach Ltd Instruction decoder using an instruction set identifier to determine the decode rules to use.
US8914615B2 (en) 2011-12-02 2014-12-16 Arm Limited Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format
WO2013132767A1 (ja) * 2012-03-09 2013-09-12 パナソニック株式会社 プロセッサ、マルチプロセッサシステム、コンパイラ、ソフトウェアシステム、メモリ制御システムおよびコンピュータシステム
US9442730B2 (en) 2013-07-31 2016-09-13 Apple Inc. Instruction source specification
RU2584470C2 (ru) * 2014-03-18 2016-05-20 Федеральное государственное учреждение "Федеральный научный центр Научно-исследовательский институт системных исследований Российской академии наук" (ФГУ ФНЦ НИИСИ РАН) Гибридный потоковый микропроцессор
RU2556364C1 (ru) * 2014-03-18 2015-07-10 Федеральное государственное бюджетное учреждение науки Научно-исследовательский институт системных исследований Российской академии наук (НИИСИ РАН) Гибридный микропроцессор
GB2540971B (en) 2015-07-31 2018-03-14 Advanced Risc Mach Ltd Graphics processing systems
US11169802B2 (en) 2016-10-20 2021-11-09 Intel Corporation Systems, apparatuses, and methods for fused multiply add
GB2563580B (en) * 2017-06-15 2019-09-25 Advanced Risc Mach Ltd An apparatus and method for controlling a change in instruction set
JP7037289B2 (ja) 2017-06-26 2022-03-16 三菱重工業株式会社 制御切替装置、プラント、制御切替方法およびプログラム

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5317240A (en) * 1976-07-31 1978-02-17 Toshiba Corp Controller
JPS583040A (ja) * 1981-06-30 1983-01-08 Nec Corp 情報処理装置
JPS59501684A (ja) * 1982-10-22 1984-10-04 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン 目的命令ストリ−ムへ殆んど実時間で插入するためのソ−スおよび目的命令ストリ−ムの外部における加速式命令写像
JPS6133546A (ja) * 1984-07-25 1986-02-17 Nec Corp 情報処理装置
JPH0689269A (ja) * 1991-02-13 1994-03-29 Hewlett Packard Co <Hp> プロセッサの制御装置、プロセッサの休止装置およびそれらの方法
GB2263565B (en) * 1992-01-23 1995-08-30 Intel Corp Microprocessor with apparatus for parallel execution of instructions
JPH0683615A (ja) * 1992-09-02 1994-03-25 Fujitsu Ltd 命令セットエミュレーションを行う計算機
US5392408A (en) * 1993-09-20 1995-02-21 Apple Computer, Inc. Address selective emulation routine pointer address mapping system
US5481684A (en) * 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor

Also Published As

Publication number Publication date
TW242678B (en) 1995-03-11
CN1147306A (zh) 1997-04-09
JP2001142697A (ja) 2001-05-25
RU2137184C1 (ru) 1999-09-10
WO1995030187A1 (en) 1995-11-09
DE69503046T2 (de) 1999-01-28
GB9408873D0 (en) 1994-06-22
KR100327777B1 (ko) 2002-03-15
DE69503046D1 (de) 1998-07-23
CN1088214C (zh) 2002-07-24
KR970703010A (ko) 1997-06-10
KR100323191B1 (ko) 2002-06-24
US5568646A (en) 1996-10-22
IN189950B (ko) 2003-05-17
IL113134A0 (en) 1995-06-29
JP3592230B2 (ja) 2004-11-24
GB2289354A (en) 1995-11-15
EP0758463B1 (en) 1998-06-17
JP3171201B2 (ja) 2001-05-28
MY114381A (en) 2002-10-31
EP0758463A1 (en) 1997-02-19
GB2289354B (en) 1997-08-27
JPH09512651A (ja) 1997-12-16
KR100327778B1 (ko) 2002-03-15

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