ID28834A - Prosesor sinyal reproduksi - Google Patents

Prosesor sinyal reproduksi

Info

Publication number
ID28834A
ID28834A IDW00200101260A ID20011260A ID28834A ID 28834 A ID28834 A ID 28834A ID W00200101260 A IDW00200101260 A ID W00200101260A ID 20011260 A ID20011260 A ID 20011260A ID 28834 A ID28834 A ID 28834A
Authority
ID
Indonesia
Prior art keywords
signal processor
reproduction signal
reproduction
processor
signal
Prior art date
Application number
IDW00200101260A
Other languages
English (en)
Inventor
Toru Aoki
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of ID28834A publication Critical patent/ID28834A/id

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6566—Implementations concerning memory access contentions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1866—Error detection or correction; Testing, e.g. of drop-outs by interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2921—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes wherein error correction coding involves a diagonal direction
    • H03M13/2924—Cross interleaved Reed-Solomon codes [CIRC]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Detection And Correction Of Errors (AREA)
IDW00200101260A 1999-09-10 2000-09-08 Prosesor sinyal reproduksi ID28834A (id)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25673699 1999-09-10

Publications (1)

Publication Number Publication Date
ID28834A true ID28834A (id) 2001-07-05

Family

ID=17296739

Family Applications (1)

Application Number Title Priority Date Filing Date
IDW00200101260A ID28834A (id) 1999-09-10 2000-09-08 Prosesor sinyal reproduksi

Country Status (7)

Country Link
US (1) US6912682B1 (id)
JP (1) JP2003516598A (id)
KR (1) KR100430657B1 (id)
CN (1) CN1155965C (id)
ID (1) ID28834A (id)
TW (1) TW512320B (id)
WO (1) WO2001020607A1 (id)

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US7120836B1 (en) * 2000-11-07 2006-10-10 Unisys Corporation System and method for increasing cache hit detection performance
US20040047209A1 (en) * 2000-11-22 2004-03-11 Chuen-Der Lien FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same
US7278083B2 (en) * 2003-06-27 2007-10-02 International Business Machines Corporation Method and system for optimized instruction fetch to protect against soft and hard errors
US9459960B2 (en) 2005-06-03 2016-10-04 Rambus Inc. Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation
US7831882B2 (en) 2005-06-03 2010-11-09 Rambus Inc. Memory system with error detection and retry modes of operation
KR100668678B1 (ko) * 2005-12-09 2007-01-12 한국전자통신연구원 부반송파 할당 방식에 혼재된 수신 신호를 복조하는 직교주파수 분할 다중 시스템의 단말 복조 장치 및 방법
US7562285B2 (en) 2006-01-11 2009-07-14 Rambus Inc. Unidirectional error code transfer for a bidirectional data link
US20070271495A1 (en) * 2006-05-18 2007-11-22 Ian Shaeffer System to detect and identify errors in control information, read data and/or write data
US8352805B2 (en) 2006-05-18 2013-01-08 Rambus Inc. Memory error detection
KR100813630B1 (ko) * 2007-02-07 2008-03-14 삼성전자주식회사 독출 성능을 향상할 수 있는 플래시 메모리 시스템 및그것의 독출 방법
US7924523B2 (en) * 2007-12-21 2011-04-12 Lsi Corporation Frequency domain approach for efficient computation of fixed-point equalization targets
JP5178844B2 (ja) 2007-12-21 2013-04-10 エルエスアイ コーポレーション 記録チャネルにおける適応等化のためのシステムおよび方法
KR20100004792A (ko) * 2008-07-04 2010-01-13 삼성전자주식회사 손상된 정보를 저장하는 방법, 손상된 정보를 저장할 수있는 정보 처리 장치, 손상된 정보를 저장 가능하게송신하는 정보 저장 장치, 손상된 정보를 저장하기 위한소프트웨어가 기록된, 정보 처리 장치로 읽을 수 있는 매체
US7924518B2 (en) * 2008-08-27 2011-04-12 Lsi Corporation Systems and methods for adaptive write pre-compensation
US9281908B2 (en) * 2008-10-08 2016-03-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for memory efficient signal and noise estimation
US7948702B2 (en) * 2008-12-18 2011-05-24 Lsi Corporation Systems and methods for controlling data equalization
US8154815B2 (en) * 2008-12-18 2012-04-10 Lsi Corporation Systems and methods for generating equalization data using shift register architecture
US7929240B2 (en) * 2008-12-18 2011-04-19 Lsi Corporation Systems and methods for adaptive MRA compensation
US7965467B2 (en) * 2008-12-18 2011-06-21 Lsi Corporation Systems and methods for generating equalization data
US7974030B2 (en) 2008-12-23 2011-07-05 Lsi Corporation Systems and methods for dibit correction
US7948699B2 (en) * 2009-01-02 2011-05-24 Lsi Corporation Systems and methods for equalizer optimization in a storage access retry
US7969337B2 (en) * 2009-07-27 2011-06-28 Lsi Corporation Systems and methods for two tier sampling correction in a data processing circuit
US8139305B2 (en) * 2009-09-14 2012-03-20 Lsi Corporation Systems and methods for timing and gain acquisition
US8854752B2 (en) 2011-05-03 2014-10-07 Lsi Corporation Systems and methods for track width determination
US8762440B2 (en) 2011-07-11 2014-06-24 Lsi Corporation Systems and methods for area efficient noise predictive filter calibration
US9112538B2 (en) 2013-03-13 2015-08-18 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for loop feedback
US8848776B1 (en) 2013-03-25 2014-09-30 Lsi Corporation Systems and methods for multi-dimensional signal equalization
US8929010B1 (en) 2013-08-21 2015-01-06 Lsi Corporation Systems and methods for loop pulse estimation
US11361839B2 (en) 2018-03-26 2022-06-14 Rambus Inc. Command/address channel error detection

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JP3284900B2 (ja) * 1996-10-18 2002-05-20 松下電器産業株式会社 データ復号方法
JPH10124995A (ja) * 1996-10-22 1998-05-15 Sony Corp データアクセス制御装置および方法
JP3710232B2 (ja) * 1996-10-24 2005-10-26 株式会社リコー 信号処理回路
KR19980065723A (ko) 1997-01-14 1998-10-15 김광호 디지탈 비디오 디스크 시스템의 데이타 처리 방법 및 장치
KR100223634B1 (ko) 1997-01-15 1999-10-15 윤종용 고속 데이타 처리 및 전송을 위한 에러정정용 메모리를 구비하는 시스템 디코더 및 에러정정용 메모리 제어방법
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Also Published As

Publication number Publication date
TW512320B (en) 2002-12-01
KR20010080966A (ko) 2001-08-25
WO2001020607A1 (en) 2001-03-22
US6912682B1 (en) 2005-06-28
JP2003516598A (ja) 2003-05-13
KR100430657B1 (ko) 2004-05-10
CN1155965C (zh) 2004-06-30
CN1327593A (zh) 2001-12-19

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