ID20506A - Metode dan aparat untuk enkapsulasi chip terbalik cetakan injeksi - Google Patents
Metode dan aparat untuk enkapsulasi chip terbalik cetakan injeksiInfo
- Publication number
- ID20506A ID20506A IDP980728A ID980728A ID20506A ID 20506 A ID20506 A ID 20506A ID P980728 A IDP980728 A ID P980728A ID 980728 A ID980728 A ID 980728A ID 20506 A ID20506 A ID 20506A
- Authority
- ID
- Indonesia
- Prior art keywords
- engagulation
- chip
- injection
- application
- engagulation injection
- Prior art date
Links
- 238000002347 injection Methods 0.000 title 1
- 239000007924 injection Substances 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/54—Providing fillings in containers, e.g. gas fillings
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/884,232 US5981312A (en) | 1997-06-27 | 1997-06-27 | Method for injection molded flip chip encapsulation |
Publications (1)
Publication Number | Publication Date |
---|---|
ID20506A true ID20506A (id) | 1998-12-31 |
Family
ID=25384227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IDP980728A ID20506A (id) | 1997-06-27 | 1998-05-18 | Metode dan aparat untuk enkapsulasi chip terbalik cetakan injeksi |
Country Status (6)
Country | Link |
---|---|
US (3) | US5981312A (fr) |
JP (1) | JP3313067B2 (fr) |
HU (1) | HUP0003638A3 (fr) |
ID (1) | ID20506A (fr) |
PL (1) | PL337808A1 (fr) |
WO (1) | WO1999000834A2 (fr) |
Families Citing this family (73)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6228688B1 (en) * | 1997-02-03 | 2001-05-08 | Kabushiki Kaisha Toshiba | Flip-chip resin-encapsulated semiconductor device |
US6001672A (en) | 1997-02-25 | 1999-12-14 | Micron Technology, Inc. | Method for transfer molding encapsulation of a semiconductor die with attached heat sink |
US5981312A (en) * | 1997-06-27 | 1999-11-09 | International Business Machines Corporation | Method for injection molded flip chip encapsulation |
US6495083B2 (en) | 1997-10-29 | 2002-12-17 | Hestia Technologies, Inc. | Method of underfilling an integrated circuit chip |
US6324069B1 (en) * | 1997-10-29 | 2001-11-27 | Hestia Technologies, Inc. | Chip package with molded underfill |
US6395584B2 (en) | 1998-12-22 | 2002-05-28 | Ficta Technology Inc. | Method for improving the liquid dispensing of IC packages |
JP2000294692A (ja) * | 1999-04-06 | 2000-10-20 | Hitachi Ltd | 樹脂封止型電子装置及びその製造方法並びにそれを使用した内燃機関用点火コイル装置 |
JP2003500833A (ja) * | 1999-05-14 | 2003-01-07 | ヘスティア・テクノロジーズ・インコーポレーテッド | モールドアンダーフィルを有するチップパッケージ |
US6490166B1 (en) * | 1999-06-11 | 2002-12-03 | Intel Corporation | Integrated circuit package having a substrate vent hole |
US6232667B1 (en) * | 1999-06-29 | 2001-05-15 | International Business Machines Corporation | Technique for underfilling stacked chips on a cavity MLC module |
KR100298829B1 (ko) | 1999-07-21 | 2001-11-01 | 윤종용 | 칩 사이즈 패키지의 솔더 접합 구조 및 방법 |
KR20010011322A (ko) * | 1999-07-27 | 2001-02-15 | 김영환 | 콘택 형성 방법 |
JP2001044137A (ja) * | 1999-08-04 | 2001-02-16 | Hitachi Ltd | 電子装置及びその製造方法 |
US6338981B1 (en) * | 1999-08-16 | 2002-01-15 | Nordson Corporation | Centrifugally assisted underfill method |
JP3485507B2 (ja) * | 1999-10-25 | 2004-01-13 | 沖電気工業株式会社 | 半導体装置 |
US6309908B1 (en) * | 1999-12-21 | 2001-10-30 | Motorola, Inc. | Package for an electronic component and a method of making it |
US6982192B1 (en) * | 1999-12-30 | 2006-01-03 | Intel Corporation | High performance thermal interface curing process for organic flip chip packages |
US20020014702A1 (en) | 2000-03-10 | 2002-02-07 | Nazir Ahmad | Packaging structure and method |
US7547579B1 (en) | 2000-04-06 | 2009-06-16 | Micron Technology, Inc. | Underfill process |
JP4120133B2 (ja) | 2000-04-28 | 2008-07-16 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
US6391682B1 (en) * | 2000-06-21 | 2002-05-21 | Siliconware Precision Industries Co., Ltd. | Method of performing flip-chip underfill in a wire-bonded chip-on-chip ball-grid array integrated circuit package module |
US6838319B1 (en) * | 2000-08-31 | 2005-01-04 | Micron Technology, Inc. | Transfer molding and underfilling method and apparatus including orienting the active surface of a semiconductor substrate substantially vertically |
US6632704B2 (en) * | 2000-12-19 | 2003-10-14 | Intel Corporation | Molded flip chip package |
US6518096B2 (en) * | 2001-01-08 | 2003-02-11 | Fujitsu Limited | Interconnect assembly and Z-connection method for fine pitch substrates |
US20020093109A1 (en) * | 2001-01-12 | 2002-07-18 | Kline Eric Vance | Composition and method for containing metal ions in electronic devices |
US6772512B2 (en) * | 2001-01-13 | 2004-08-10 | Siliconware Precision Industries Co., Ltd. | Method of fabricating a flip-chip ball-grid-array package without causing mold flash |
US6545869B2 (en) * | 2001-01-17 | 2003-04-08 | International Business Machines Corporation | Adjusting fillet geometry to couple a heat spreader to a chip carrier |
JP2002270638A (ja) * | 2001-03-06 | 2002-09-20 | Nec Corp | 半導体装置および樹脂封止方法および樹脂封止装置 |
US7220615B2 (en) | 2001-06-11 | 2007-05-22 | Micron Technology, Inc. | Alternative method used to package multimedia card by transfer molding |
CA2350747C (fr) * | 2001-06-15 | 2005-08-16 | Ibm Canada Limited-Ibm Canada Limitee | Moulage par transfert ameliore de boitiers de circuits integres |
JP3711333B2 (ja) * | 2001-07-27 | 2005-11-02 | 沖電気工業株式会社 | 半導体装置の製造方法および樹脂封止装置 |
US6519844B1 (en) * | 2001-08-27 | 2003-02-18 | Lsi Logic Corporation | Overmold integrated circuit package |
US6963142B2 (en) * | 2001-10-26 | 2005-11-08 | Micron Technology, Inc. | Flip chip integrated package mount support |
DE10250541B9 (de) * | 2002-10-29 | 2004-09-16 | Infineon Technologies Ag | Elektronisches Bauteil mit Unterfüllstoffen aus Thermoplasten und Verfahren zu dessen Herstellung |
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-
1997
- 1997-06-27 US US08/884,232 patent/US5981312A/en not_active Expired - Fee Related
-
1998
- 1998-05-18 ID IDP980728A patent/ID20506A/id unknown
- 1998-06-08 JP JP15971498A patent/JP3313067B2/ja not_active Expired - Fee Related
- 1998-06-12 HU HU0003638A patent/HUP0003638A3/hu unknown
- 1998-06-12 PL PL98337808A patent/PL337808A1/xx unknown
- 1998-06-12 WO PCT/GB1998/001729 patent/WO1999000834A2/fr not_active Application Discontinuation
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1999
- 1999-01-12 US US09/228,601 patent/US6369449B2/en not_active Expired - Fee Related
-
2002
- 2002-04-08 US US10/118,395 patent/US6570261B2/en not_active Expired - Lifetime
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US5981312A (en) | 1999-11-09 |
PL337808A1 (en) | 2000-09-11 |
JP3313067B2 (ja) | 2002-08-12 |
HUP0003638A2 (hu) | 2001-02-28 |
US20020111016A1 (en) | 2002-08-15 |
US20010045637A1 (en) | 2001-11-29 |
US6369449B2 (en) | 2002-04-09 |
US6570261B2 (en) | 2003-05-27 |
WO1999000834A3 (fr) | 1999-06-10 |
WO1999000834A2 (fr) | 1999-01-07 |
JPH1126484A (ja) | 1999-01-29 |
HUP0003638A3 (en) | 2001-03-28 |
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