GB2410375A

GB2410375A - DRAM capacitor electrodes

Info

Publication number: GB2410375A
Application number: GB0500294A
Authority: GB
Inventors: Byung-Jun Park
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2002-06-27
Filing date: 2003-06-24
Publication date: 2005-07-27
Anticipated expiration: 2023-06-24
Also published as: GB2410372B; GB2410376B; GB2410373B; GB0500291D0; GB2410374B; GB2410373A; GB0500294D0; GB2410374A; GB2410372A; GB0500293D0; GB2410375B; GB0500290D0; GB0500295D0; GB2410376A

Abstract

The storage electrode comprises a number of vertically extending fins 261 separated by silicon oxide 271. The fins and oxide structures are formed by fabricating polysilicon and silicon oxide spacer structures in a mould oxide pattern 196.

Description

24 1 0375 SEMICONDUCTOR MF,MORY DEVICES AND METHODS FOR MANUFACTURING THE

SADIE USING SIDEWAI,L SPACERS

Field of tile Invention

The present invention relates to semiconductor memory devices and methods for manutacturinO the same, and more particularly to storage nodes tor semiconductor memory devices and methods for manufacturing the same.

Background ot the 11lveIltion

As semiconductor memory devices have become highly integrated, the areas ot unit cells and the distances between cells may be reduced. However, capacitors having a large capacitance witless small areas are desired, to provide predetermined capacitances. As Is well known to those having skill in the art, semiconductor memory device capacitors mclutle a lower electrode, also referred to as a storage node electrode, an upper electrode, also referred to as a plate electrode, and a dielectric layer therebetween. Conventional methods for securing large capacitances of the capacitors Include using a high dielectric material as the dielectric layer, reducing the 1 > thickness of a dielectric layer, and/or increasing the surface area of storage node electrodes of the capacitors.

A method tor increasing the surface area of the storage node electrodes includes fonnmO three-drmensional storage node electrodes, for example, cylindrical or concave electrodes.

FIG. I Is a sectional view illustrating conventional concave storage node electrodes.

Referring to FIG. 1, an interlevel insulating layer 12 is formed on a senconductor substrate 10 having circuit devices (not shown), such as MOS transistors lDc mterlevel nsulatin,, layer 12 includes storage node contact plugs 14 2: tliat are rdely known to connect a source region (not shown) of a selected MOS transistor with storage node electrodes 16, which will be formed in a subsequent process Thereafter, the cp-shaped concave storage node electrodes 16 are formed on the predctennmed portions of the storage node contact plugs 14 and the interlevel msulatmg layer 12. A method for forming the concave storage node electrodes 16 is as follows First, a mold oxide layer (not shown) having a predetenmmed thickness Is dcposted on the interlevel insulating layer 12 mcludmg the storage node contact plaits 14 The mold oxide layems etched into hole shapes until exposing the storage node contact Stags 14, thereby defimng a region for for-min the storage node electrodes Thereafter, a concltctive layer (not shown) and a node isolation insulating layer (not shown) are scrbseqtently formed on the mold oxide layer so as to contact the exposed storage node contact plugs 14. The condtrctve layer and the node isolation msulatu1g layer are chenncal mechanical polished to expose the surface of.

the mold oracle layer. '['hereafter, the node isolation msulatirlg layer and the mold oxide layer are removed by a conventional method so that the concave storage node l O electrodes 16 are Conned.

However, the concave storage node electrodes formed by the above-descnbed method may have the following problems.

In order to manul.'acture the storage node electrodes havmg large capacitance, the liciaht of the storage node electrodes may need to be increased within a limited area hi addition, n1 order to increase the height of the storage node electrodes, the tlncliness of the mold oxide layer may need to be increased. In this case, when the mold oxide layer is etched to define the region for forming the storage node electrocles, a large slope may occur on the sidewalls of the holes, and the critical dimension of the exposed storage node contact holes may be reduced. Accordingly, the lower portions of the thin and high storage node electrodes may become narrower so that the storage node electrodes may become twistable. In addition, the distance between adjacent storage node electrodes may be reduced so that it may be difficult to provide insulation between the storage node electrodes.

Furtl1errnore, due to thermal stress generated in subsequent processes, some of the weak storage node electrodes may fall or break and generate bridges between unit storage node electrodes, thereby casing defects in the device.

Summary of the Invention

An aspect of the present invention provides a semiconductor memory device 3() conprsn, a semcondtrctor stbstr-ate, an mterlcvel msulatmg layer on the semiconductor substrate, storage node contact plugs in the interlevel insulating layer, and storage node electrodes, which comprise a plurality of conductive line patterns separated n1 predetenmmed intervals while havmg a predetermined height, contacting the stowage node contact plugs, wherein, the storage node electrodes are separated by insulating line patterns between selected storage node electrodes in tenets of a unit eel] of the memory device.

Another aspect of the present invention provides a semiconductor memory device comprising an mterlevel msulatnlg layer on a semiconductor substrate ncludmg a plurality of active regions, a plurality of word Lee structures passing over the active regions, source and dram regions on the active regions at respective sides of the word lnc structures, and a plurahty of bit hne structures crossing the word line strctru-es, electrically connecting to the drain regions, and passing between the active regions; etch stoppers on the mterlevel insulating layer; storage node contact plugs formed in the interlevel insulating layer and the etch stoppers; storage node electrodes, which compose a plurality of conductive line patterns separated in predetermined Intervals while having a predetemnned hergllt, contacting lo the storage node contact plugs; and supporters between the storage node electrodes and extending perpendicular to an extending direction of the line patterns of the storage node electrodes. In these embodiments, the plurality of line patterns are fonned mto straight hoes.

Another aspect of the present invention provides a semiconductor memory device comprrsng an nterlevel msulatng layer on a semiconductor substrate including a plurality of active regions, a plurality of word line structures passing over 9() the active regions, source and drain regions on the active regions at respective sides of the word One structures, and a plurality ol bit hne structures crossing the word line structures, electrically connecting to the drain regions, and passing between the active regions; etch stoppers on the interlevel insulating layer; storage node contact plugs in the mterlevel insulating layer- and the etch stoppers; storage node electrodes, which comprise a plurality of conductive Brie patterns separated In the same intervals while having a specific height, contacting the storage node contact plugs; and supporters between the storage node electrodes while being perpendicular to an extending direction of the line patterns of the storage node electrodes. In these embodiments, the plurality of lme patterns are Donned in the shape of waves In a plan view.

In another aspect of the present wlverltron, there are provided methods of manctactunn<, a semiconductor memory device. In these methods, an mterlevel Slate layer Is deposited on a semiconductor substrate, and a plurality of storage node contact plugs are formed In the rnterlevel insulating layer In specific intervals Thereafter, mold oxide layerpatterns are formed on the interlevel msulatmg layer in specific Intervals to expose the storage node contact plugs, and the spaces between the mold oracle layer patterns are tilled by alternately fornng conductive line patterns and msulatmg Imc patterns, repeatedly, on the sidewalls of the mold oxide layer patterns. Grooves are t'ormed perpendicular to the mold oxide layer patterns by etching portions of the mold oxide layer patterns, the conductive One patterns, and the msrlatmg lure patterns Storage node electrodes are for-mea by selectively removing the mold oxcle layer patterns and the insulate, line patterns.

to a yet further aspect of the present invennon, there are provided methods for manct'acturng a semiconductor memory device. in these methods, a semiconductor substrate, which includes a plurality of active regions, a plurality of word brie structures passing over the active regions, source and drain regions fonned on the active regroups at respective sides of the word line structures, and a plurality of bit line structures crossing the word brie structures, electrically connecting to the drain regions, and passing between the active regions, is prepared. An nterlevel insulating layer is formed on the semiconductor substrate, etch stoppers are formed on the n1terlevel insulating layer, and storage node contact plugs are formed in the mterlevel nsulatmg layer and the etch stoppers at specific intervals. Thereafter, a plurality of mold oxide layer patterns are formed on the etch stoppers at specific intervals to expose the storage node contact plugs The spaces between the mold oxide layer 2() patterns are f fled by alternately forming at least one conductive line pattern and n1sulatng One pattern on the sidewalls of the mold oxide layer patterns in order to follow the shape of the mold oxide layer patterns. (grooves are formed perpendicular to the mold oxide layer patterns by etching portions of the mold oxide layer patterns, the conductive line patterns, and the insulating line patterns. Thereafter, supporters are formed m the grooves, and storage node electrodes are bombed by selectively renovmg the mold oxide layer patterns and the insulating hne patterns [n these embodiments, the mold oxide layer patterns extend into straight lines and the mold oxide layer patterns and the supporters separate the storage node electrodes in units of each cell.

[n a still other aspect ol'the present invention, there are provided methods for manrtacturmg a semiconductor memory device. In these methods, a semiconductor substrate, which includes a plurality of active regions, a plurahty of word hne structures passing over the active regions, source and drain regions formed on the active regions at respective sides of the word One structures, and a plurality of bit line structircs crossing the word One structures, electrically connecting to the drain regions, and passing between tile active regions, IS prepared. An interlevel msulatmg layer is formed on the semiconductor substrate, and etch stoppers are formed on the nterlevel insulating layer Thereat'ter, storage node contact plugs are formed in the mterlevel insrlatmg layer and the etch stoppers at specific intervals, and a plurahty of mold oxide layer patterns, which are t'ormed in the shape of waves on a plan view, are f'ormecl on the etch stoppers to expose the storage node contact plugs The spaces between the mold oxide layer patterns are filled by alternately forming at least one conductive line pattern and Insulating Ime pattern on the sidewalls of'the mold oxide layer patterns n1 order to t'ollow the shape of the mold oxide layer patterns.

I'hereaf'ter, grooves are romped perpendicular lo the mold oxide layer patterns by etching portions of the mold oxide layer patterns, the conductive Ime patterns, and the insrlatm:, One patterns. Supporters are formed m the grooves, and storage node electrodes are t'ormed by selectively removing the mold oxide layer patterns and the msrlatmg line patterns. In these embodiments, the mold oxide layer patterns and the srppor-ters separate the storage node electrodes in units of each cell.

Another aspect of the present invention provides a storage node t'or a senncorldrctor memory device which includes a pair of spaced apart mold oxide layer patterns on a semiconductor memory device substrate that defines t'acmg mold oxide layer patten1 sidewalls. A pair of first conductive spacers are provided, a respective one of which is on a respective one of the tracing mold oxide layer pattern sidewalls and t'ace one another. A pair of first nsrlatmg spacer is provided, a respective one of which Is on a respective one of the pair of first conductive spacers, opposite the respective one of the t:acmg mold oxide layer pattern sidewalls A pair of second COlidLlCtlVe SpaCel S IS provided, a respective one of which IS on a respective one of the pair of first nsulatng spacers, opposite the respective one of the pair of first conductive spacers. At least one second insulating spacer is provided between the pair of second conductive spacers. In some embodiments, a single insulating spacer extends between the pair of second conductive spacers.

3() Storage nodes may be t:abrcated according to some embodiments of the present invention by formmg spaced apart mold oxide layer patterns on a semiconductor memory device substrate that define facmg mold oxide layer pattern sidewalls A first conductive spacer is formed on each ofthe facmg mold oxide layer pattern sidewalls A first msulatmg spacer Is formed on each of the first conductive s spacers. A second conductive spacer Is formed on each of the t'irst msulatmg spacers and at least a second Insulating spacer is formed on the second conductive spacers. In some embodiments, the first conductive spacers, the first msulatng spacers and the second conctuctive spacers are formed by conforrnally t'orming a conductive or msulatmg layer on the t'acmg mold oxide layer pattern sclewalls and on the senuconcluctor memory device substrate therebetween, and then amsotropcally etching the conductive or Insulators, layer to remove at least some the layer that is on the semiconductor memory device substrate tilerebetween.

In other embodiments of'the invention, a storage node for a semiconductor memory device includes a plurality of freestanding storage node electrodes that project away from a semiconductor memory device substrate by a first distance. A supporter Is configured to support at least one ofthe freestanding storage node electrodes and projects away Tom the semiconductor memory substrate by a second distance that Is less than the first distance. In other embodiments, the plurality of t'reestanding storage nodes extend along two spaced apart rows, and the supporter extends between the two spaced apart rows. Storage nodes may be tabncated by forming the freestanding storage node electrodes and then forming the supporter to support at least one of the t'reestandmg storage node electrodes.

2() Briet'Description ot' the Drawings

FIG I Is a sectional view illustrating a conventional semiconductor memory device havmg concave storage node electrodes; F IGS 2A through 2D are plan views ol'stages in the manufacture of a semiconductor memory device according to first embodiments of the present invention, FIGS 3A through 3C are sectional views of stages ha the manul;acture of a semiconductor memory device according to tile first embodiments of the present invention, FIG, 4 is a perspective view Illustrating a semiconductor memory device 3() according to the t'irst embodiments ot'the present Invention, FIG 5 Is a plan view 11ustratmg a modified semiconductor memory device accords to the first embodiments of the present invention; FIGS. 6A through 6D are plan views of stages m the manufacture of a semiconductor memory device according to second embodiments of the present mventon, FIGS. 7A and 7B are sectional views of stages m the manul'acture of a semiconductor memory device according to the second embodrrnenis of the present mventon; FIG 8 Is a perspective view r11ustratng a semiconductor memory device according to the second embodiments of the present invention; FIG. 9 Is a plan view 11stratrng a modified semiconductor memory device accorclin, to the second embodunents ofthe present invention; FIGS. I ()A tllroigh I OC are sectional views of stages m the manufacture of a semiconductor memory device according to third embodiments of the present Invention, FIGS. I I A through I I D are plan views of stages m the manufacture of a semiconductor memory device according to fourth embodiments of the present invention; FIGS. I 2A and 12B are sectional views of stages m the manufacture of a semiconductor memory device according to the fourth embodiments of the present invention; 2() FIGS. 13 and 14 are perspective views illustrating a sen:lieonduetor memory device according to the fourth embodiments of the present invention; FIG 15 is a plan view illustrating a modified semiconductor memory device aeeorclmg to the t'orrth embodiments of the present invention; FIG 16 Is a plan view illcrstratm another modified semiconductor memory clevce according to the fourth embodiments of the present Invention; FIGS. I 7A and 1 7B are plan views of stages m the manul'acture of a semiconductor memory device according to fil'th embodiments of'the present mveilron, and FIG 18 Is a plan view illustrating a modified semiconductor memory device according to the fifth embodiments of the present mventon

Detailed Description

Tile present invention now will be deserbed more Lilly hereinafter with reference to the accompanying drawings, In which embodiments of the invention are shown However, this Invention should not be construed as hmited to the embochments set forth herein Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled n1 the art In the drawings, the thclcness of layers and regions are exaggerated for clarity Like nrrnbers refer to like elements throughout.

It will be understood that when an element such as a layer, region or substrate is referred to as bemg "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or mtervenlng elements may also be present.

In contrast, when an element is referred to as being "directly on" or extending I () "directly onto" another element, there are no ntervemrlg elements present First Embodiments Referring to FIGS 2A and 3A, an isolation layer 110 is formed In a selected region ova semiconductor scbstr-ate 100 by a conventional STI rnethocl, thereby defining active regions 115 on which devices will be formed. Here, the semiconclrctol substrate 100 may be a silicon substrate including P-type or N-type mpcrties and may include wells m a predeterrnned region to form a device. The active regions 115, f'onned in, for example, a bar shape, are spaced apart by a predetermined distance in rows and columns. Here, the active regions 115 are arranged to alternate by each row. In other words, the spaces between the adjacent active regions 115 correspond to the central portions of the active regions of the srbsecl:rent row n1 the direction of the longer axis of the active regions 115. Here, the central portions of the active regions will be dram regions.

Thereafter, word line structures 120 are fonnecl on the semiconductor substrate 100. Here, the word line structures 120 are extended to be parallel with one another while being perpendicular to the longer axis of the active regions 115 In addition, a pair of word line structures 120 may be arranged for each of the active regions 115. Sor-ce and drain regions (not shown) are formed m the active regions fit both sides of the word line structures 120 by a conventional method.

3() A first nterlevel Insulating layer 130 is formed on the semiconductor substrate having the word line structures 120 and on the source and dram regions. First and second contact pads 140a and 140b, whacks contact the source and dram regions while having the same height as the first interlevel Insulating layer 130, are fonned In the fh-st iterlevel Insulating layer 130. A method for forming the first and second contact pads 140a and 140b will now be described. After the first mterlevel insulating layer 130 Is formed, the first interlevel insulating layer 130 is etched to expose the source and dram regions. A conductive layer, for example, a doped polysilcon layer, Is deposited to contact the exposed source and dram regions, and the cc:'nductve layer is etched back car chemical mechanical polished so as to expose the surface of the first nterlevel nsulatmg layer 130 Accordingly, the first and second contact pads 140a and 140b are t'ormcd F1ere, the first and second contact pads 140a and 140b contact the dram region and the source regions, respectively.

A second nterlevel isolating layer 150 Is Conned on the first mterlevel nslatmg layer 130 and bit hne structures 165 are t'ormed on the second mterlevel insclatnlg layer ISO. Here, the bit Ime stnchre 165 includes a bit line 160, a mask layer 162 formed on the bit line 160, and spacers 164 formed on both walls of the bit One 160 and the mask layer 162. The mask layers 162 and the spacers 164, t'orrned of; t'or example, silicon nitride layers, are formed to surround the bit lines 160 In order to t'orrn selE-aDgned contact holes when f'onning storage node contact holes. In addition, In some embodiments, the bit One structures 165 are formed to be perpendicular to the word One structures 120 and that the bit line structures 165 are arranged on the Isolation layer 110 between the active regions 115 while being parallel to the longer axis of the active regions. Here, though not shown in the drawings, bit line contact plugs for connecting the first contact pads 140a and the bit hate structures 165 are f'onned In the second interlevel insulating layer 150 by a conventional method, before t'orming the bit One structures 165.

A third interlevel nsulatmg layer 170 and etch stoppers 175 are sequentially Conned on the second mterlevel insulating layer 150 having the bit line structures 165.

Here, the first through thrcl interlevel insulating layers 130, 150, and 170 may be formed ot', for example, Insulating layers of the shcon oxide layer group. The etch stoppers 175 are t'ormecl of insulating layers, for example, swoon nitride layers, having an etchm,, selectivity dit'ferent from the etching selectivtres of the second and the-d mterlevel msulatng layers 150 and 170. The etch stoppers 175, the third nterlevel msulatmg layer 17O, and the second mterlevel insulating layer 150 are etched to expose the second contact pads 140b, which contact the source regions, so that storage node contact holes 180 are fomled Here, the storage node contact holes are t'omed by a sel t:ahgnmg method usmg the bit hne structures 165 Thereafter, a conductive layer, for example, a doped polyshcon layer, is deposited to suf'fcently fill the storage node contact holes 180, and the doped polysiDcon layer Is chemical mechamcal poNsl1ed to expose the etch stoppers 175 Accordingly, storage node contact plugs 185 are Conned Other conventional technrclues for t'ormmg a semcondtctor memory device substrate may be used.

A mold oxide layer is formed on the storage node contact plugs 185 and the etch stoppers 175 to a predetemlned thickness. In some embodiments, the mold oxide layer for determining the height of the storage node electrodes Is formed to a heft higher than the desired height of the storage node electrodes by a predetermined height, consdenng that the mold oxide layer will be chemical neclamcal polished to the predetermined height in the present embodiments. The mold oxide layer is etched to overlap the bit One structures 165so that mold oxide layer patten1s 190 are formed Here, the mold oxide layer patterns 190 can be L'onmed m predetermined intervals, Nor example, one-ptch or two-pitch. The mold oxide layer patterns 190 of FIG 2A are arranged m two-pitch intervals and the mold oxide layer ]5 patterns 190 of FIG 5 are arranged in one-pitch intervals. In this respect, the mold oxide layer patterns 190 in the two-pitch intervals mean that two storage node contact plugs 185 are located between two adjacent mold oxide layer patter-es 190. In addition, the line wrath of the mold oxide layer patterns 190 may be equal to or less than the hne width of the bit line structures 165.

Referring to FIG. 3B, a conductive layer for the storage node electrodes, for example, a polyshcon layer, is deposited on the etch stoppers 175 on which the mold oxide layer patterns 190 are t'onned. Next, the polysrUcon layer is ansotropically etched to fond conductive spacers 200 oL'polysilicon on both walls of the mold oxide layer patterns 190 An insulating layer is deposited on the resultant structure and ansolropcally etched to forth nsulatnlg spacers 220 on the sidewalls of the conductive spacers 200 By repeatedly forming the conductive spacers 200 and the nsclatn, spacers 220, the spaces between the mold oxide layer patterns 190 are filled Here, in order to separate unit cells, the last spacers fowled between the mold oxide layer patterns 190, i.e., the spacers formed at the center points between the mold oxide layer patterns 190, are the insulating spacers 220. In addrtorl, the conductive spacers 200 are formed to contact the node contact plugs 185. In the present enlbodnents, the spaces between the mold oxide layer patterns 190 are filled by f'omlmg the conductive spacers 200 twice and l'ormmg the insulating spacers 220 twice, however, the widths and the numbers of the conductive spacers 200 and the insulating spacers 220 can be varied Rci'en-m;, to FIGS 2B and 3C', the upper surfaces of the mold oxide layer patterns 19O, the conductive spacers 200, and the insulating spacers 220 are chemical mecllancal polished to planarze the upper surfaces so that conductive hoe patterns 201 and isolating hne patterns 221 and 225 are fowled between mold oxide layer patterns 191 Here, reference numeral 191 denotes the mold oxide layer patterns having plananzed upper surfaces. And, the conductive line patterns 201 are the conductive spacers 220 having planarzed upper surfaces, and the nsulatmg brie patterns 221 and 225 are the nsulatnig spacers 220 havmg plananzcd upper surfaces.

The conductive line patterns 201 respectively contact the storage node contact plugs and the insulating hne patterns 221 and 225 insulate the conductive line patterns 201. In particular, the insulating line patterns 225 formed on the etch stoppers 175 separate the conductive One patterns 201 by one pitch, he, the size of unit cells, in a direction parallel to the bit hne structures 165 while insulating the conductive line patterns 201. In the present embodiments, each of the storage node contact plugs 185 includes, for example, two conductive line patterns 201 and one Insulating hne pattern 221 therebetween.

Ret'erung to FIG. 2C, in order to define the storage node electrodes, grooves 2() 230 are fowled by patterning portions of the mold oxide layer patterns 191, the conductive One patterns 201, and the insulating brie patterns 221 and 225. Here, the grooves 230 extend to be perpendicular to the extending direction of the mold oxide layer patterns 191, i.e., to be parallel to the word hne structures 120 The grooves 230 are formed between the word hne structures 120 on which the drain regions are " 25 formed In order to secure maximum storage node electrode regions. In other words, a couple of'word hoes 120 are arranged between a couple of adjacent grooves 230 such that the grooves 23() open the etch stoppers 175.

Rel'ernng to FIGS. 2D and 4, an insulating layer t'or supporters is deposited to sufficiently bury the grooves 230, and the insulating layer Is etched to a height smaller 3() than the height ol'the conductive brie patterns 201 so as to form supporters 240. Here, the nsulatmg layer for supporters is formed of an insulating layer having an etching selectivity clt'ferent t'ron1 the etchmg selectvties of the mold oxide layer patterns 191 and the insulating hne patterns 221 and 225. Accordingly, the insulating layer Is wet etched to forth the supporters 240.

Smce the supporters 240 are formed in the grooves 23O, the supporters 240 cross through the conductive brie patterns 201 so that the supporters 240 separate the conductive Lee patterns 201 accordm;, to cell Furthermore, the supporters 24() support the conductive One patterns 201, thereby reducing or preventing the conductive brie patterns 201 lrom falling or bending toward the adjacent conductive hne patterns 201. In addition, the supporters 240 have a height smaller than the height of the conclcctve hne patterns 201 in order to secure storage node electrode capacitance.

Thereafter, the mold oxide layer patterns 191 and the rnsrlatrng One patterns 221 and 225 are removed by a conventional wet etching method.Here, since the mold oxide layer patterns 191 and tile insilatmg line patterns 221 and 225 have the etching selectivity clilferent from the etching selectrvites of the etch stoppers 175 and the supporters 240, the mold oxide layer patterns 191 and the msrlatmg brie patterns 221 and 225 are selectively removed. Thins, tile storage node electrodes 250 formed of the plrrahty of conductive hne patterns 201 are completely formed.

The storage node electrodes 250 according to the present embodiment are formed of a plurality of conductive line patterns 201 having a fine line width so as to increase the surface area of the storage node electrodes 250. In addition, the scppor-ters 240 separate and support the storage node electrodes 250 according to cell 2() so as to reduce or prevent the storage node electrodes 250 from falhng or bending toward the adjacent storage node electrodes 250. Frrthennore, as shown in FIG. 2D, the storage node electrodes 250 are extended to the regions corresponding to the dram regions (not shown) as well as the regions having the bit line structures 165 so as to increase the surface area of the storage node electrodes 250 Second Embodllllellts Referring to FIGS. 6A and 7A, an isolation layer 110 is formed on a sernrcondrctor substrate 100 as shown in the first embodiment to define active regions 115. Word 3() hne structures 120 are lonned on the semiconductor substrate 100 as follows. After sbseclrently depostng a gate nsclatn1g layer 121, word Ones 123, and a hard mask layer 125' the layers are patterned to be perpendicular to the longer axis of the active regions 115 Word One spacers 127 are formed on the sidewalls of the patterned hard mask layers 125 and word hnes 123 by a conventional method to form the word hne structures 120 Here, the hard mask layers 125 and the word line spacers 127 are formed of silicon mtndc layers lavmg an etching selectivity dt'ferent t'rom the etchin;, selectivity of an mterlevel msuiatng layer of a silicon oxide layer group, which will be t'ormed to form sell:algnmg contact holes m a subsccluerit process. In addition, the word One structures 120 extend so as to be parallel with one another and a couple of word line structures 120 are arranged on each active region 115 Source and dran1 regions (not shown), a first mterlevel insulating layer 130, contact pads 140a and 140b, a second mterlevel msulatng layer 170, etch stoppers 175, and storage node contact pads 185 are formed no the active regions 115 at both sides of the 1() word hoe structures 120 by the method illustrated m the first embodnent.

A mold oxide layer Is formed on the storage node contact plugs 185 and the etch stoppers 175 lo a predetermined thickness. As described above, the mold oxide layer t'or determining the height ol' the storage node electrodes is formed to a height higher than the desired height ol the storage node electrodes by a predetermined I S height The portion of the mold oxide layer is etched to expose the storage node contact plugs 185, thereby f'ormmg mold oxide layer patterns 195 In the present embodiments, the mold oxide layer patterns 195 are arranged to be parallel to the word brie structures 120 while overlapping the dram regions of the active regions 115.

In addition, the mold oxide layer patterns 195 can be formed in predetennmed intervals, t'or example, one-ptch or two-pitch The mold oxide layer patterns 195 ot' FIG. 6A are arranged m two-ptch Intervals, and the mold oxide layer patterns 195 of FIG 9 are arranged in one-ptch intervals. Here, the mold oxide layer patterns 195 in the two-ptch intervals mean that two storage node contact plugs 185 are located between two adjacent mold oxide layer patterns 195, and the mold oxide layer patterns 195 In the one-pitch intervals mean that one storage node contact plug 185 is located between two adjacent mold oxide layer patterns 195.

Referring to FIGS (jB and 7B, a conductive layer for the storage node electrodes, t'or example, a doped polyslicon layer, is deposited on the etch stoppers on which the mold oxide layer patterns 195 are f'orrned as shown In the first 3() enbodmient. The polyslcon layer Is amsotropically etched lo forth conductive spacers (not shown) of polysilicon on the both walls of the mold oxide layer patterns 195. An Insulating layer Is deposited on the resultant structure and amsotropcally etched to fonm insulating spacers (not shown) on the sidewalls of the conductive spacers By repeatedly f'ormmg the conductive spacers and the Insulating spacers, the spaces between the mold oxide layer patterns 195 are filled. Here, the condtctivc spacers contact the storage node contact pltigS 185 and the last spacers are the nstilaimg, spacers 'I'he last spacers are donned on the etch stoppers 175 between the storage node contact Stags 185 and the last spacers may have relatively larger One wraith than the other mstilatmg spacers. In the present embodiments, each of'the spaces between the mold oxcle layer patterns 195 is filled by torment the condtrctve spacers f'otir tmles and t'omlmg the mstlating spacers voter times; however, the widths and the Octobers of' the conductive spacers and the insulating spacers can be controlled.

The tipper strrfaces of the mold oxide layer patterns 195, the condtrctrve spacers, and the insulating spacers are chemical mechanical polished to t'om1 conductive One patterns 261 and nstrlatmg line patterns 271 and 275 between mold oxide layer patterns 196 Here, ret'erenee numeral 196 denotes the mold oxide layer patterns wits planarizecl tipper surfaces. The condtetve hne patterns 261, which are the conductive spacers having plananzed upper surtaxes, contact the storage node contact plugs 185. The insulating line patterns 271 on the storage node contact plugs 185, which are the msulatmg spacers 220 having plananzed upper surfaces, Insulate the conductive line patterns 261. In addition, the Insulating line patterns 275 formed on the etch stoppers 175 insulate the conductive hne patterns 261 and separate the conductive line patterns 261 in a direction parallel to the word line structures 120 by one pitch, e., cell unit. In the present inver1tior1, four conductive lme patterns 261 contact each of the storage node contact plugs 185 Referring to FIG. 6C, m order to define the storage node electrodes In each cell, grooves 235 are formed by patterning portions of the mold oxide layer patterns 2: 196, the conductive lme patterns 261, and the nsulatrr1g brie patterns 271 and 275 Here, the grooves 235 are t'onned to overlap the bit hne structures 165 Accordingly, grooves 235 and the nsulatmg spacers 275 separate the conductive line patterns 261 n1 units of isn't cell.

Refernng to FIGS 6D and 8, an msulatmg layer for supporters is deposited to sufficiently fill the grooves 235, and the insulating layer is etched to a height smaller than the height of the conductive line patterns 261 so as to form supporters 245. In some embodiments, the nsulatmg layer filled m the grooves 235 is formed of an nstilatmg layer having an etching selectivity different from the etchmg selectvites of the mold oxide layer patterns 196 and the insulating hue patterns 271 and 275. Since the supporters 245 cross through the conductive brie patterns 261, the supporters 245 separate the concluctve line patterns 261 according to cell Further-more, the supporters 245 prevent the conductive line patterns 261 from falling or benclng toward the adjacent conductive One patterns 261 In addition, the supporters 245 are fonned to a her,ht smaller than the height ofthe conductive lme patterns 261 m order to secure storage node electrode capacitance Thereal'ter, the mold oxide layer patterns 196 and the Insulating brie patterns 271 and 275 are removed by a conventional wet etching method. Ilere, since the mold oracle layer patterns 196 and the insulating line patterns 271 and 275 have an I O etching selectivity different frown the etching selectivties of the etch stoppers 17S and the supporters 245, the mold oxide layer patterns 196 and the msulatmg line patterns 271 and 275 are selectively removed. Thus, storage node electrodes 280 are camp feted.

Tile ef't'ects of the second embociiments can be the same as those of the first embodiments.

l'lllrcl Embodiments FIGS. I OA tllrorgll 10C are sectional views of stages in the manufacture of a semiconductor memory device according to third embodiments of the present hlventon. The descriptions of the elements that are the same as the first and second ernbodunerlts will not be repeated, and the same reference numerals are allotted for the same elements ol'the first and second embodiments. In addition, the present embodiments include a method for forrnmg storage node electrodes where the processes performed up until forming mold oxide layer patterns are the same as the processes of the first embodiments, thus the description will begin with the subsequent processes.

Referring to FIG. IOA, a first conductive layer 310 for storage node electrodes is formed on etch stoppers 17S on which mold oxide layer patterns 190 are formed.

Thereafter, an msulatmg layer 320 Is deposited on the first conductive layer 310.

3() The first conductive layer 310 and the insulating layer 320 are anrsotropcally etclied to Down first conductive spacers 311 and insulating spacers 321 as shown m FIG I OB A second conductive layer 330 for storage node electrodes Is deposited on the resultant str-uchire. Here, the first conductive spacers 311 contact storage node contact plugs 18S.

Next, by amsotropcally etching the second conductive layer 330, second condictrve spacers (not shown) are formed on the sidewalls of the insulating spacers 321 Here, the second concluctve spacers contact the storage node contact plugs 185 while contacting the sidewalls of the first conductive spacers 311. As shown in FIG. 1 ()C, tile surt'ace of the resultant structure Is chemical mechanical polished to form first conductive One patterns 312 t'ormed of the first conductive spacers 311 and second conductive brie patterns 332 formed of the second conductive spacers Here, the first conductive brie patterns 312 are formed into an L-shape and portions of'the second conductive hne patterns 332 contact the lower portions of the first conductive 1() line patterns 317 1'11ereaf'ter, the insulating spacers 321 and the mold oxide layer patterns 1')0 are removed by a conventional wet etching method. Accordmgly, storage node electrodes 300 formed of the first and second conductive brie patterns 312 and 332 are f'oned.

Here, the storage node electrodes 300 are formed of two conductive line patterns, however, the wraths and the numbers of'the conductive hue patterns can be varied In addition, the mold oxide layer is formed to be parallel to the bit One structures in the present embodiments; however, the mold oxide layer can be formed to be parallel to the word lme structures as shown In the second embodiments.

Fourth Embodlmellts FIG 12A and I 2B are the sectional views cut along lines C-C' of FIGS 11 A and l l B. respectively.

The descriptions of the elements that are the same as the first through third embodiments will not be repeated, and the same reference numerals are allotted for the same elements of the t'irst through third embodiments. In addition, in the present embodiments, the processes performed up until forming storage node contact plugs are the same as the processes of the first through third embodiments, thus the description will beam with the subsequent processes.

Referring to FIGS. 11 A and 12A, a mold oxide layer is formed on storage node contact plugs 185 and etch stoppers 175 to a predetermined thickness Here, the mold oxide layer for detennrmng the height of'storage node electrodes can be formed to the desired height of the storage node electrodes. Thereat'ter, portions of the mold oxide layer are dry etched to forth a plurality of mold oxide layer patterns 400. Here, the mold oxide layer patterns 400 are formed in, for example, one-ptch intervals, while being formed in the shape of waves on a plan view. In other words, ridge portions LYE of the mold oxide layer pattenrs 400 located between the storage node contact pi ups 185 and valley portions X, of the mold oxide layer patterns 400 are loc,ited on dram regions, winch correspond to first contact pads 140a, or on an Isolation layer ll0 conespondng to the dram regions When connecting the ridge portions A' of tile wave- shaped mold oxide layer patterns 400, straight Ones are formed. In addition, m some embodiner1ts, the straight lines are parallel to bit Ones strrctres 165.

As shown in FIGS. l lB and 12B, a conductive layer 410 t'or storage node electrodes, for example, a coped polysiLcon layer, is deposited on etch stoppers 175 on which the wave-shaped mold oxide layer patterns 400 are formed, and a bluffer Slating layer 420 is cleposted on the conductive layer 410 for storage node electrodes. Thereafter, a chemical mecl1anrcal polishing is performed to expose the l 5 mold oxide layer patients 400 Accordmgly, the conductive layer 410 for storage node electrodes remains In a region defined by the mold oxide layer patterns 400.

Here, the sidewalls of the remain, conductive layer 410 for storage node electrodes have the same wave shape as the mold oxide layer patterns 400.

Next, as shown In FIGS. l lC and 13, grooves 430 are formed by dry etching 2() portions of the mold oxide layer patterns 400, the conductive layer 410 t'or storage node electrodes, and the rrlscrlatng layer 420 In order to separate the storage node electrodes by cell. Here, the grooves 430 are fonmed between word hne structures 120, on which drain regions (not shown) are formed, while being perpendicular to the extending direction of the mold oxide layer patterns 400, he, the direction of bit One structures. It Is preferable that the grooves 430 pass throrgll the valley portions X, of the mold oxide layer patterns 400.

Thereal-'ter, as shown m FIGS l l D and 14, an insulating layer for supporters is deposited to sut'licently f It the grooves 430 Here, the msulatrr1g layer t'or supporters can be t'omled of the same rratenal as the etch stoppers 175, t'or example, a sihcon Betide layer The insulating layer is wet or dry etched to a predeterrmrned thickness so that the Insulating layer is remained In the grooves 430 to a height smaller than the her,ht of the conductive layer 410 for storage node electrodes or the mold oxide layer patterns 400 Accordingly, supporters 440 are t'ormecl.

The mold oxide layer patterns 400 and the insulating layer 420 are removed by a convcntrorlal wet etching method to form storage node electrodes 425 Here, since the etch stoppers 175 are for-mecl on the resrltarlt strrctcire on the semiconductor substrate 100 and the etching selectivity ofthc supporters 440 Is different from the etching selectvtres of tile mold oxide layer patterns 400 anal the msrlating layer 420, only the mold oxide layer patten1s 400 and the insirlatmg layer 420 are selectively removed Theirs, the storage node electrodes 425 are defined m mats of each cell. In other words, the storage node electrodes 425 are separated m mats of each cell by the supporters 440 m a diction parallel to the word lines. In addition, the supporters 440 t'orn1ed in specific intervals support the storage node electrodes 425, which are formed into wave-sl1aped line patterns. Therefore, the narrow and high storage node electrodes 425 are prevented from t'alLng toward the adjacent storage node electrodes According to the present embodiments, since the storage node electrodes 425 are formed m the wave shape, the srrf:ace area of the storage node electrodes 425 increases. In addition, since the storage node electrodes 425 are extended to the drain regions or the regions corresponding to the drain regions, the surface area of the storage node electrodes 425 further increases.

Frrtl1ermore, since the supporters 440 are formed to separate the storage node electrodes 425 m units of each cell, the storage node electrodes 425 are reduced or prevented from Calling or bending toward the adjacent storage node electrodes 425.

Here, the mold oxide layer patterns can be formed by changing the intervals of the wave as shown in FIG. 15 Referring to FIG 15, mold oxide layer patterns 450 are formed in the shape of waves In a plan view Here, ridge portions X3 and valley portions X4 are formed to be located between storage node contact plugs 185. In this case, lines formed by connectrr1g the ridge portions X3 and hales formed by connecting the valley portions X4 are parallel with one another by a predetermined distance, which is wider than the width of the active regions.

If the wave shape of the mold oxide layer patterns 450 Is changed, the same effect Is attained.

In acldtion, as shown in FIG. 16, mold oxide layer patterns 500 may be cornier in tvo-pitch rnlervals In other words, the mold oxide layer patterns 500 are arranged in two-ptch intervals as shown in the first embodrmcnt while bemg Donned n1 the shape of waves on a plan view For example, In the mold oxide layer patterns 500, ridge portions V may be located between storage node contact plugs 185, and valley portions X, may be located on drain regions, e, first contact regions, or on a isolation layer I I O corresponding to the dram regions If the mold oxide layer patterns 500 in two-pitch intervals are t'onned, the same effect is attained.

In addition, storage node electrodes 425 can be formed by the method performed n1 the third embodnents.

Frtll1 Elnbodnrlell_ I () F'1(:S l 7A and 17B are plan views of stages n1 the manrtact:rre of a senncondcctor menol-y device according to t'il'th embodiments of the present invention. 'I'he processes performed Lip until fondling etch stoppers 175 are the same as the processes of the t'irst and second cmbocliments, thus the description will begin with the subsequent processes.

l S Refen-mg to FIGS. 17A, mold oxide layer patterns 600 are t'ormed in the shape ol'waves In a plan view, on etch stoppers 175. FJere, the mold oxide layer patterns 600 can be l'omled In, t'or example, one-pitch intervals. In other words, Ones formed by connecting ridge portions Xs or valley portions X6 of the mold oxide layer patterns 600 are stbstantally parallel to word line strrctres 120 In addition, the mold oxide layer patterns 600 are formed to expose each of the storage node contact plugs 185 between the adjacent mold oxide layer patterns 600 On the scone lines The mold oxide layer patterns 600 are formed on regions wLhort storage node contact plugs, i c, on drain regions and on an Isolation layer 110 corresponding to the dram regions.

A plurality of conductive line patterns 610 and Insulating line patterns 620 are alternately Conned between the mold oxide layer patterns 600 Here, the plrraLty of conductive line patterns 610 and hsrlatng One patterns 621) are formed into waves accorded, to the wave-sl1aped mold oxide layer patterns 600. In this case, the conductive One patterns 610 and the insulating line patterns 620 are fonned by the above-descrbed methods.

3() As shown In FIG. 17B, portrol1s of the mold oxide layer patterns 600, the conductive line patterns 610, and the insulating line patterns 620 are etched to borne grooves 630 The grooves 630 are formed on regions, which overlap bit line stnchres 165, In order Lo separate tl1e conductive One patterns 610 in units of each cell Here, the conductive line patterns 610 are defined m units of each cell by the 1') grooves 630 and the mold oxide layer pattern 600, and the cond,.ct,,ve One patterns 610 are fowled into waves while contacts the storage node contact plugs 185.

Tl,,ereat'ter, supporters (not shown) arc t'ormed m the grooves 630 by the abovc-descr,bed method The mold oxide layer patterns 600 and the msulatng One patterns 620 are Etched to form storage node electrodes 625 ll'the mold oxide layer patterns 600 are formed to be parallel to the word l,,ne structures 120, the same eft'ect may be attained As shown n1 FIG 18, the same et't'ect may be attained by t'ormmg the mold oxide layer patterns 700 into waves In two-pitch intervals.

l O As described above, according to embodiments of the present ulventon, storage node electrodes are formed In a plurality of line pattern types having a fine One width. 'Linus, the surface area of the storage node electrodes can increase In adcttc,n, the supporters formed of an nsulatmg layer are formed to be perpendicular lo the extending direction of the line patterns of the storage node electrodes.

Therefore, the supporters separate the storage node electrodes in units of each cell, and the supporters support the storage node electrodes, thereby reducing or preventing the storage node electrodes from t'all''ng or bending toward the adjacent storage node electroctes Furtllernlore, the regions t'or fondling the storage node electrodes may be 2() Increased so that the surface area of the storage node electrodes may be increased.

While this mventon has been particularly shown and dcscr,bed with reference to preferred embodrnents thereof, it will be understood by those skilled in the art that various changes in Corm and details may be made therein without departing from the splint and scope of the hlvention as deemed by the appended claims to the drawings and specification, there have been disclosed typical preferred embochments ot the hlventon and, although specific terms are employed, they are crsecl in a generic and descriptive sense only and not t'or purposes of limitation, the scope of the nventon being set forth In the t'ollowmg claims.

Claims

CLAIMS:.

I A storage node for a semiconductor memory device comprsmg a pair of spaced apart mold oxide layer patterns on a semiconductor memory device substrate that define facing mold oxide layer pattern sidewalls, a pair of first condtrctrve spacers, a respective one of which Is on a respective one of the tacmg mold oxide layer pattern sidewalls and face one another; a pair of first insulating spacers, a respective one of whacks Is on a respective one ol the pan- of tnst condictve spacers, opposite the respective one of the lacing look! oxide layer patting sidewalls; ] () a pair of second conductive spacers, a respective one of which is on a respective one of the pair of first instigating spacers, opposite the respective one ol the pair of first conductive spacers; and at least one second Insulating spacer between the pair of second conductive spacers 2 A storage node according to Claim I wherein the at least one nslatmg spacer is a smgle insLrlatm spacer that extends between the pair of second conductive spacers.

SO 3 A method of tabncatulg a storage node for a semiconductor memory device compusmg tormmg spaced apart mold oxide layer patterns on a semiconductor memory device substrate that define [;acmg mold oxide layer pattern sidewalls; tonging a tnst conductive spacer on each ofthe facing mold oxide layer pattern sidewalls; fonnrnc, a first insulating spacer on each of the first conductive spacers, opposite the respective one of the tacmg mold oxide pattern sidewalls, forming a second conductive spacer on each of the first msulatmg spacers, opposite the respective one of the pair of first conductive spacers; and forming at least one second msulatmg spacer between the pair of second conductive spacers 4 A method according to Clams 3 wherem the forming a first conductive spacer comprises confonnally forming a first conductive layer on each of the facing mold oxide layer pattern sidewalls and on the semiconductor memory device substrate tlerebetween, and amsotropcally etching the first conductive layer to remove at least some of the first conductive layer that Is on the semiconductor memory device substrate therebetween to define the first conductive spacers A method according to Claim 4 whcrem the forming a first nsulatmg spacer comprises.

1() conformally tonnmg a first msulatmg layer on each of the first conductive spacers and on the semiconductor memory device substrate therebetween; and amsotropcally etching the first insulating layer to remove at least some ofthe first insulate, layer that Is on the semiconductor memory device substrate therebetween to define the first insulating spacers. i5

6 A method according to Claim 5 wherein the forming a second conductive spacer comprises: confonmally Donning a second conductive layer on each of the first insulating spacers and on the semiconductor memory device substrate therebetween; and 2() amsotropically etching the second conductive layer to remove at least some of the second conductive layer that is on the semiconductor memory device substrate tllerebetween to den no the second conductive spacers.