GB2410376A

GB2410376A - DRAM capacitor electrode

Info

Publication number: GB2410376A
Application number: GB0500295A
Authority: GB
Inventors: Byung-Jun Park
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2002-06-27
Filing date: 2003-06-24
Publication date: 2005-07-27
Anticipated expiration: 2023-06-24
Also published as: GB0500293D0; GB2410374B; GB2410375A; GB2410373A; GB2410374A; GB0500290D0; GB2410376B; GB2410373B; GB0500294D0; GB2410372A; GB0500295D0; GB0500291D0; GB2410372B; GB2410375B

Abstract

An insulating supporting structure 240 extends between rows of DRAM storage electrodes 250. The supporting structure prevents the storage electrodes falling over and contacting adjacent electrodes.

Description

24 1 0376 SF.\IICONDUCTOR MF.MORY DEVICES AND METHODS FOR

)'IANUE;ACI'(IRING TI-II: SAME USING SIDEWAL1, SPACERS

Field of the Invention

The present n1venlon relates to semiconductor memory devices and methods for manLifactunnO the san1e, and more particularly to storage nodes for semicondLctor memory crevices and methods for manufacturing the same.

Backaround of the invention

As semcon Victor rnenory devices have become highly integrated, the areas of unit cells and the distances between cells may be reduced. However, capacitors having a large capacitance wthn: small areas are desired, to provide predetermined capacitances. As Is well known to those having skill in the art, semiconductor memory device capacitors include a lower electrode, also referred to as a storage node electrode, an upper electrode, also referred to as a plate electrode, and a dielectric layer therebetween. Conventional methods for secrmg large capacitances of the capacitors include using a Ogle dielectric material as the dielectric layer, reducing the thickness of a clelectnc layer, and/or increasing the surface area of storage node electrodes of the capacitors.

A method for mcreasng the surface area of the storage node electrodes includes conning three-dimensonal storage node electrodes, for example, cylndncal or concave electrodes.

E; IG] is a sectional view llustratr1g conventional concave storage node electi-odes.

Referring to FIG 1, an interlevel insulating layer 12 Is formed on a semconcluctor substrate 10 having circuit devices (not shown), such as MOS transistors The nterlevel nsulatmg layer 12 Includes storage node contact plugs 14 that are widely known to connect a source region (not shown) of a selected MOS tr-ansstor with storage node electrodes 16, which will be formed in a subsequent process Thereafter, the cLp-shaped concave storage node electrodes 16 are fon1led on the prcdete1mnccl portions ol the storage node contact plugs 14 and the mterlevel insulate layer 12 A method for fonnnO the concave storage node electrodes 16 is 3() as follows First, a mold oxide layer (not shown) having a predetermined thickness is deposited Oil the mterlevel insulating layer 12 including the storage node contact plugs 14 The mold oxide layer is etched into hole shapes until exposing, the storage noble contact plugs 14, thereby defining a region t'or forming the storage node electrodes Thereat'ter, a conductive layer (not shown) and a node isolation insulating layer (not shown) are subsequently t'ormed on the mold oxide layer so as to contact the exposed storage node contact plugs 14 The conductive layer and the node isolation insulating layer ale chcmcal mechanical polshecl to expose the surface ot' the mold oxide layer Thereafter, the node isolation insulating layer and the mold oxide layer are removed by a conventional method so that the concave storage node l () electrodes 16 are t'ormed.

However, the concave storage node electrodes formed by the above-descrbed method may have the following problems.

In order to manufacture the storage node electrodes havmg large capacitance, the height ot'the storage node electrodes may need to be increased withy a limited area. in addition, in order to increase the height of the storage node electrodes, the thickness of the mold oxide layer may need to be increased. In tiers case, when the mold oxide layer is etched to define the region for t'onning the storage node electrodes, a large slope may occur on the sidewalls of the holes, and the cntcal dnnenson of the exposed storage node contact holes may be reduced. Accordmgly, the lower portions of the thin and high storage node electrodes may become narrower so that the storage node electrodes may become unstable. In addition, the distance between adjacent storage node electrodes may be reduced so that it may be dit'ficult to provide isolation between the storage node electrodes.

Furtl1enore, due to thermal stress generated in subsequent processes, some of 2: the weak storage node electrodes may tall or break and generate bridges between unit storage node electrodes, thereby causmg defects in the device.

Summary ol'the Invention

An aspect ol'the present invention provides a semiconductor memory device comprising a semiconductor substrate, an nterlevel insulating layer on the semiconductor substrate, storage node contact plugs m the mterlevel msulatmg layer, and storage node electrodes, which comprise a plurality of conductive hne patterns separated in predetenmmed intervals while having a predeterrnmed height, contacting the storage node contact plugs, wherein, the storage node electrodes are separated by insulating, line patterns between selected storage node electrodes in units of a umt cell of the memory device Another aspect of the present invention provides a semiconductor memory device compnsmg an mterlevel msulatmg layer on a semcondiietor substrate neluclmg a plurality of active regions, a plurahty of word hne structures passing over the active regions, source and dram regions on the active regions at respective sides of the word brie structures, and a plurality of bit line structures crossing the word brie structures, electrically connection;, to the drain regions, and passmg between the active regions; etch stoppers on the mterlevel insulating layer; storage node contact plugs l() tongued in the mierlevel insulating layer and the etch stoppers; storage node electrodes, which comprise a plurality of conductive One patterns separated h1 precletemned Intervals while having a predetermined height, eontaetmg to the storage node contact plugs, and supporters between the storage node electrodes and extending perpendicular to an extending direction ofthe hne patterns of the storage node electrodes In these embodiments, the plurality of line patterns are formed mto straight hoes Another aspect of the present invention provides a semiconductor memory device compusmg an rnterlevel rnsulatmg layer on a semiconductor substrate ineludrlg a plurahty of active regions, a plurality of word line structures passing over the active regions, source and drain regions on the aetrve regions at respective sides of the word line structures, and a plurality of bit line structures crossing the word Ime structures, electrically eonneetmg to the dram regions, and passing between the active regions; etch stoppers on the nterlevel msulatmg layer; storage node contact plugs nl the utterly vel h1sulatng layer and the etch stoppers; storage node electrodes, which comprise a plurahty of conductive idle patterns separated m the same intervals while have, a spectic hegllt, contacting the storage node contact plugs; and supporters between the storage node electrodes while being perpendicular to an extending :lrectron of the idle patterns of the storage node electrodes. In these embodiments, the plurality of brie patterns are Conned In the shape of waves m a plan view In another aspect ot the present invention, there are provided methods of manufacturing a semcondtctor memory device In these methods, an mterlevel msulatul layer Is deposited on a semiconductor substrate, and a plurality of storage nocie contact plugs are torrmed in the nterlevel insulating layer m speclic intervals Thereatter, mold oxide layer patterns are formed on the mterlevel insulating layer In l specific intervals to expose the storage node contact plugs, and the spaces between the mold oxide layer patten1s are filled by alternately forming' conductive One patterns and nsulatmg brie patterns, repeatedly, on the srclewalls of the mold oxide layer patterns Grooves are formed perpendc. 'lar to the mold oxide layer patterns by etching portions ot'the mold oxide layer patterns, the conductive hne patterns, and the mlsulatmY, line patterns Storage node electrodes are formed by selectively removing the infold oxide layer patterns and the msrlatmg hne patterns In a yet t'rrther aspect of the present mventron, there are provided methods for manl'acturrnY, a semiconductor memory device. In these methods, a semiconductor I () substrate, whrcl1 includes a plurality of active regions, a plurality of word One strrchrres passing, over the active regions, source and dram regions fon-rlecl on the active regions at respective sides of the word line structures, and a plurality of bit line structures crossing the word One structures, electrically connecting to the dram reV,ons, and passing between the active regions, is prepared An mterlevel insulating layer is formed on the semiconductor substrate, etch stoppers are formed on the rnterlevel msulatlg layer, and storage node contact plugs are termed m the interlevel msrlatirlg layer and the etch stoppers at specific intervals. Thereafter, a plurality of mold oxide layer patterns are formed on the etch stoppers at specific intervals to expose the storage node contact plugs. The spaces between the mold oxide layer patterns are filled by alternately forming at least one conductive hne pattern and Insulatm;, hne pattern on the sidewalls of the mold oxide layer patterns In order to t'ollow the shape of the mold oxide layer patterns. Grooves are formed perpendicular to the mold oxide layer patterns by etching, portions of the mold oxide layer patterns, the conductive lime patterns, and the insulating hne patterns Thereat'ter, supporters are t'orrned in the grooves, and storage node electrodes are formed by selectively rernovmg the mold oxide layer patterns and the msulatng brie patterns. In these embodiments, the mold oxide layer patterns extend mto straight Ones and the mold r:>xrtie layer- patterns and the supporters separate the storage node electrodes in units of eacl cell 3() In a still other aspect of the present mventron, there are provided methods for manut:acturmg a sem,condctor memory device. In these methods, a semiconductor suhslrate, which includes a plur-aUty oi'active regions, a plurality of word brie structures pass,, over the active regions, source and dram regions formed on the active re,Y,ons at respective sides of the word hne structures, and a plurahty of bit line strtctrres crossing, the word lme structures, electrically cornectng to the drain regions, and passing between the active regions, is prepared. An mterlevel insulating layer is formed on the semiconductor substrate, and etch stoppers are t.ormed on the mterlevel insulating layer. Tllereat'tcr, storage node contact plugs are formed In the S mterlevel nsulatmg layer and the etch stoppers at specific Intervals, and a plurality of mold oxide layer pattems, which are formed m the shape of waves on a plan view, are formed on the etch stoppers to expose the storage node contact plw;, s. The spaces between tile mold oxide layer patterns are filled by alternately forming at least one coidcctve Me pattern and insulating One pattern on the sclewalls of the mold oxide I () layer patterns m order to follow the shape of the mold oxide layer patterns Thereafter, grooves are formed perpendicular to the mold oxide layer patterns by etching portions of the mold oxide layer patterns, the conductive line patterns, and the msulatrlg hne patterns. Supporters are formed In the grooves, and storage node electrodes are t'ormed by selectively removing the mold oxide layer patterns and the insulatm, hoe patterns. In these embodiments, the mold oxide layer patterns and the supporters separate the storage node electrodes in units of each cell.

Another aspect of the present invention provides a storage node for a semiconductor memory device which includes a pair of spaced apart mold oxide layer patterns on a semiconductor memory device substrate that defines t'acing mold oxide layer pattern sidewalls A pair of first conductive spacers are provided, a respective one of which is on a respective one of the facing mold oxide layer pattern sidewalls and t'ace one another A pair of t'irst insulating spacer Is provided, a respective one of which Is on a respective one of the pair of first conductive spacers, opposite the respective one of the facing mold oxide layer pattern sidewalls. A pair of second conductive spacers is provided, a respective one of which Is on a respective one of the pair of first insrlatmg spacers, opposite the respective one of the pair of t'irst conductive spacers. At least one second msulatmg spacer Is provided between the pan of second conductive spacers In some embodiments, a single insulating spacer exten as between the pair of second conductive spacers.

Storage nodes may be fabricated according to some embodiments of the present invention by formmg spaced apart mold oxide layer patterns on a semiconductor memory device substrate that define facing mold oxide layer pattern sidewalls A first conductive spacer Is conned Ott each ol the i:acmg mold oxide layer pattern sidewalls A t'irst nsulatmg spacer is t'omled on each of the first conductive spacers A second conductive spacer is fonned on each of the first insulating spacers and at least a second insalatmg spacer Is fonned on tile second conductive spacers. In some emtotlnrlerlts, the first conductive spacers, the first msrlatn spacers and the second conductive spacers are formed by conlorrmally forming a conductive or mslatn, layer on the tacmg mold oxide layer pattern sidewalls and on the semiconductor memory device substrate therebetween, and then amsotropically etching the conductive or nsrlatmg layer to remove at least some the layer that is on the semiconductor memory device substrate therebetween.

In other embodiments of the mventon, a storage node tor a semiconductor memory device includes a plrraLty of freestanding storage node electrodes that project away from a semiconductor memory clevce substrate by a first distance. A supporter Is configured to support at least one of the fieestandmg storage node electrodes and projects away from the semiconductor memory substrate by a second distance that is less than the first distance. In other embodiments, the plurality of IS Ireestandn:, storage nodes extend along two spaced apart rows, and the supporter extends between the two spaced apart rows Storage nodes may be fabricated by form, the freestanding storage node electrodes and then forming the supporter to support at least one of the treestandmg storage node electrodes.

2() Brief Description of the Drawines

FIG I Is a sectional view illustrating a conventional semiconductor memory device having concave storage node electrodes; FIGS. 2A through 2D are plan views of stages m the manufacture of a semiconductor rnen1ory device according to first embodiments of the present invention, FIGS 3A through 3C are sectional views ot stages n1 the manufacture of a senconductor memory device according to the first embodanerlts of the present nlvellllor1, FIG 4 Is a perspective view illustrating a semiconductor memory device 3() according to the first embodiments of the present mventon; FIG 5 is a plan view rilustratng a modified semiconductor memory device tccormg to the tarot embodrnents of the present invention; FIGS 6A through 6D are plan views of stages m the manufacture of a semrconcluctor memory device according to second embodiments of the present mventron, FIGS 7A and 7B are sectional views of stages in the rnanrl'actrre of a semiconductor memory device according to the second embodiments of the present mventron, FIG 8 Is a perspective view 11strating a semrcorldrctor memory device according to the second embodiments of the present Invention; FIG. 9 is a plan view illustrating a modified semiconductor memory device I O accords, to the second emhodrT?lents of the present Invention; FIGS 1 OA through I OC are sectional views of stages in the manut'acture of a semiconductor memory device according to third embodiments of the present invention; FIGS. 11 A through I I D are plan mews ot'stages in the manufacture of a semiconductor memory device according to t'ourth embodiments of the present invention, FIGS. I 2A and 1 2B are sectional views of stages in the manufacture of a semiconductor memory device according to the fourth embodiments of the present Invention; 2() FIGS 13 and 14 are perspective views illustrating a semiconductor memory device according to the fourth embodiments ofthe present invention; FIG. 15 is a plan view illustrating a modified semiconductor memory device according to the t'ourth embodiments of the present invention; FIG 16 Is a plan view rllustratmg another modified semiconductor memory device according to the fourth embodiments of the present Invention; FIGS. I 7A and 1 7B are plan views of stages in the rnanuf;acture of a semiconductor memory device according to fil'th embodiments of the present mventron; and FIG. 18 is a plan view Illustrating a modified semiconductor memory device 3() according to the f fth embodiments of the present invention

Detailed Description

The present Invention now will be described more fully hereinat'ter with reference to the accompanying drawings, m which embodiments of the Invention are shown. However, this invention should not be construed as hmited to the embedments set forth herein. Rather, these embodiments are provided so that tiers disclosure will be thorough and complete, and will frilly convey the scope ol the invention to those skilled In the art. In the drawings, the thickness ol layers and regions are exaggerated for clarity Like numbers refer to hlce elements throughout It will be understood that when an element starch as a layer, region or substrate is refened to as bemg "on" or extending "onto" another element, it can be directly on or extend clnectly onto the other element or rntervemng elements may also be present In contrast, when an element Is referred to as being "directly on" or extending I () "chrectly onto" another element, there are no ntervenmg elements present First Embodiments Refers;, to FIGS 2A and 3A, an Isolation layer 110 is fonned in a selected rcgon of a semiconductor substrate 100 by a conventional ST1 method, thereby detnmg active regions 115 on which devices will be formed. Here, the semiconductor substrate 100 may be a silicon substrate including P-type or N-type Impurities and may include wells in a predetermined region to torm a device. The active regions 115, formed in, for example, a bar shape, are spaced apart by a predetermined distance in rows and columns. Here, the active regions 115 are arranged to alternate by each row. In other words, the spaces between the adjacent active regions 115 correspond to the central portions of the active regions of the subsequent row In the direction of the longer axis of the active regions 115. Here, the central pontoons of the active regions will be drain regions Thereatter, word hne structures 120 are formed on the semiconductor ?5 substrate 100 here, the word hne structures 120 are extended to be parallel with one another while being perpendicular to the longer axis of the active regions 115. In addition, a pair of word line structures 120 may be arranged for each of the active regions 1 15 Source and drain regions (not shown) are torrned m the active regions 1 15 at both sides of the word One structures 120 by a conventional method.

A first nterlevel msulatmg layer 130 is formed on the semiconductor substrate havmg the word hne structures 120 and on the source and dram regions First and second contact pads 140a and 140b, which contact the source and drain regions while having the same he,ht as the first nterlevel insulating layer 130, are funned m the first mterlevel Insulating layer- 130 A method for forming the first and second contact pads 140a and 140b will now be described. After the first mterlevel nsclatmg layer 130 Is conned, the first rnterlevel insulating layer 130 Is etched to expose the source and drain regions. A conductive layer, t'or example, a doped polyshcon layer, Is deposited to contact the exposed source and dram regions, and the conductive layer is etched back or chemeal mechanical polished so as to expose the surface of the first nterlevel nsulatmg layer 130 Accordingly, the t'irst and second contact pads 140a and 140b are fon1lecl. Here, the first and second contact pads 140a and 140b contact the drain region and the source regorls, respectively A second mterlevel insulating layer 150 Is formed on the first mterlevel Insulating layer 130 and bit One structures 165 are formect on the second interleveJ insulating layer 150 Here, the bit line structure 165 includes a bit brie 16O, a mask layer 162 formett on the bit line 160, and spacers 164 formed on both walls of the bit Ime 160 and the mask layer 162 The mask layers 162 and the spacers 164, formed ot; t'or example, silicon nitride layers, are termed to surround the bit Ones 160 m order ' to for-m selt:ah,ned contact holes when l'orrnmg storage node contact holes In addition, m some embodiments, the bit line structures 165 are formed to be perpendicular to the word line structures 120 and that the bit lme structures 165 are arranged on the isolation layer 110 between the active regions 115 whi le being parallel to the longer axis of the active regions. Here, though not shown in the drawings, bit brie contact plugs for connecting the first contact pads 140a and the bit hne structures 165 are formed m the second rnterlevel insulating layer 150 by a conventional method, before fonnmg the bit hne structures 165.

A third mterlevel insulating layer 170 and etch stoppers 175 are sequentially formed on the second rnterleve1 insulating layer 150 having the bit line structures 165.

Here, the first through third nterlevel insulating layers 130, 150, and 170 may be formed of, t'or example, Insulating layers of the silicon oxide layer group. The etch stoppers 175 are formed of h1sclatul layers, t'or example, silicon nitride layers, having an etching selectivity different from the etching selectvties of the second and thud nterlevel msulatmO layers 150 and 170. The etch stoppers 175, the third 3() n1terlevel nsulathlg layer 17O, and the second rnterlevel insulating layer 150 are etched to expose the second contact pads 140b, which contact the source regions, so that storage node contact holes 180 are formed. Here, the storage node contact holes are formed by a self:alrgnn, method using the bit line structures 165 ''1'hereaf'ter, a conductive layer, t'or example, a doped polysrlcon layer, is deposited to sufficiently fill the storage node contact holes 180, and the doped polyshcon layer Is chemical mechamcal poLslled to expose the etch stoppers 175. Accordingly, storage node contact plugs 185 are formed Oilier conventional techniques for forming a semiconductor memory device substrate may be used.

A mold oracle layer is tombed on the storage node contact plugs 185 and the etch stoppers 175 to a predetermined thickness. In some embodiments, the mold oxide layer for determmmg the height of the storage node electrodes is formed to a height higher than the desired height of the storage node electrodes by a predetemlmed hegllt, considering that the mold oxide layer will be chemical mechamcal polished to the predetermined height m the present embodiments. The mokl oxide layer is etched to overlap the hit hne structures 165 so that mold oxide layer patterns 190 are formed Here, the mold oxide layer patterns 190 can be ton-red in predetennmed intervals, for example, one-ptch or two-ptch. The mold oxide layer patterns 190 of FIG. 2A are arranged m two-pitch intervals and the mold oxide layer patterns 190 of FIG S are arranged in one-ptch intervals. In this respect, the mold oxide layer patterns 190 m the two-ptch intervals mean that two storage node contact plugs 185 are located between two adjacent mold oxide layer patterns 190. In addition, the hne width of the mold oxide layer patterns 190 may be equal to or less than the hne width of the bit line structures 165.

Referring to FIG. 3B, a conductive layer for the storage node electrodes, for example, a polysilcon layer, is deposited on the etch stoppers 175 on which the mold oxide layer patterns 190 are tonned Next, the polyslicon layer is amsotropically etched to form conductive spacers 200 of polysihcon on both walls of the mold oxide layer patterns 190 An insulating layer is deposited on the resultant structtre and anisotropcally etched lo fonm insulating spacers 220 on the sidewalls of the conductive spacers 200 By repeatedly fonnmg the conductive spacers 200 and the nsulathl spacers 220, the spaces between the mold oxide layer patterns 190 are tolled Here, nil order to separate unit cells, the last spacers formed between the mold oxide layer patterns 190, i.e., the spacers formed at the center points between the mold 3() oxide layer patterns 190, are the msulatmg spacers 220 In addition, the conductive spacers 200 are formed to contact the node contact plugs 185 In the present embodiments, the s,oaces between the mold oxide layer patterns 190 are filled by tonnmg the conductive spacers 200 twice and tonnmg the msulatmg spacers 220 twice, however, the wattles and the numbers of the conductive spacers 200 and the Slather spacers 220 can be varied Refenrmg to FIGS 2B and 3C, the upper surfaces of the mold oxide layer patients 190, the conductive spacers 200, and the insulating spacers 220 are cherubical mechanical poked to plananze the upper surfaces so that conductive hne patterns 201 and msulatrnO hnc patterns 221 and 225 are formed between mold oxide layer patterns 191. Here, reference numeral 1')1 denotes the mold oxide layer patterns having placarded upper surfaces And, the conductive one patterns 201 are the conductive spacers 220 having planarrzed upper surfaces, and the msulatmg one l O patterns 221 and 225 are the insulating spacers 220 having plananzed upper surfaces.

The condcctrvc one patterns 201 respectively contact the storage node contact plugs and the insulating hne patterns 221 and 225 insulate the conductive hne patterns 201. In particular, the insulating one patterns 225 formed on the etch stoppers 175 separate the conductive lme patterns 201 by one pitch, net, the size of'unit cells, m a direction parallel to the bit brie structures 165 while insulating the conductive hne patterns 201 In the present embodiments, each of the storage node contact plugs 185 Deludes, for example, two conductive one patterns 201 and one Insulating hne pattern 221 therebetween.

Referring to FIG 2C, in order to define the storage node electrodes, grooves 230 are formed by patterning portions of the mold oxide layer patterns 191, the conduetrve line patten1s 201, and the insulating line patterns 221 and 225. Here, the grooves 230 extend to he perpendreular to the extending direction of the mold oxide layer patterns 191, i e, to be parallel to the word hne structures 120. The grooves 230 are f'onned between the word lme struehres 120 on which the drain regions are t'onned in order to secure maximum storage node electrode regions In other words, a couple of word Ones 120 are arranged between a couple of adjacent grooves 230 such that the grooves 230 open the etch stoppers 175 Rcherrng to FIGS 2D and 4, an insulating layer for supporters is deposited to stffciently bury the grooves 230, and the rrlsulatng layer Is etched to a height smaller than the height of the eoncletrve line patterns 201 so as to form supporters 240. Flere, the rnsulatmg layer for supporters is formed of an msuiating layer having an etching selecLvty different from the eLchng selectvtres ot'the mold oxide layer patterns 191 and the rnsulatmg line patterns 221 and 225 Accordmgly, the msulatmg layer is wet etched to form the supporters 240. 1 1

Smce the supporters 240 are formed m the grooves 230, the supporters 240 cross tilroi,l1 the conclrctve hoe patterns 201 so that the supporters 240 separate the concluctve One patterns 201 according to cell Furthermore, the supporters 240 support the conductive InJe patter-es 201, thereby reducing or preventing the cQdcctve One patterns 201 from f, ZlLng or bending toward the adjacent conductive line patterns 201. In adclitron, the supporters 240 have a height smaller than the height of the conductive hne patterns 201 in order to secure storage node electrode capac i tance Thereal'ter, the mold oxicte layer patterns 191 and the Insulating One patterns 1 () 221 and 225 are removed by a conventional wet etching method. Here, since the Hold oxide layer patterns 191 and the msrlatmg lme patterns 221 and 225 have the etching selectivity different from theetching sclcctvities of the etch stoppers 175 and the supporters 240, the mold oxide layer patterns 1')1 and the insulating hne patterns 221 and 225 are selectively removed Thins, the storage node electrodes 250 formed of the plraLty of conductive line patterns 201 are completely t'ormed.

he storage node electrodes 250 according to the present embodn1ent are formed of a plurality of conductive One patterns 201 havmg a fine brie width so as to increase the surface area of the storage node electrodes 250. In addition, the supporters 240 separate and support the storage node electrodes 250 according to cell 2() so as to reduce or prevent the storage node electrodes 250 from tailing or bending toward the adjacent storage node electrodes 250 Furthermore, as shown m FIG. 2D, the storage node electrodes 250 are extended to the regions corresponding to the dram regions (not shown) as well as the regions having the bit line structures 165 so as to increase the surface area of the storage node electrodes 250.

Second Embodiments Rei'errm, to l IGS GA and 7A, an isolation layer 110 Is formed on a semiconductor substrate 100 as shown m the first embodnnent to define active regions 115. Word 3() lme structures 120 are t'ormed on the semiconductor substrate 100 as follows. At'ter subsequently depostm, a gate msulatng layer 121, word lines 123, and a hard mask layer 125, the layers are patterned to be perpendicular to the longer axis of the active regions 115 Word hne spacers 127 are formed on the sidewalls ofthe patterned hard mask layers 125 and word hues 123 by a conventional method to form the word lme structures 120. FIerc, the hard mask layers 125 and the word brie spacers 127 are l'ormed of silicon mtude layers having an etching selectivity different from the etching selcctvty of an mterlevel msulatng layer of a silicon oxide layer group, which Will be Conned to t'orn1 self-aLgmng contact holes m a subsequent process. In acldton, the word brie slnctrres 120 extend so as to be parallel with one another and a couple of word brie strrctres 120 are arranged on each active region 115 Source and dram regions (not showri), a first mterlevel mslatng layer 13O, contact pads 140a and 140b, a second mterlevel nsulatmg layer 17O, etch stoppers 175, and storage node contact pads 185 are fondled m the active regions 115 at both sides of the word hue structures 120 by the method illustrated In the first embodiment.

A mold oxide layer is formed on the storage node contact plugs 185 and the etch stoppers 175 to a predeterrnned thickness. As described above, the mold oxide layer for determining the hegllt of the storage node electrodes Is formed to a height higher than the dcsred height of the storage node electrodes by a predetermined Is height. The portion of the mold oxide layer is etched to expose the storage node contact plugs 185, thereby formmg mold oxide layer patterns 195 In the present embodiments, the mold oxide layer patterns 195 are arranged to be parallel to the word line strictures 120 while overlapping the drain regions of the active regions 115.

In addition, the mold oxide layer patterns 195 can be formed In predetermined intervals, for example, one-pitch or two-ptch. The mold oxide layer patterns 195 of FIG 6A are arranged in two-ptch intervals, and the mold oxide layer patterns 195 of FIG 9 are arranged in one-ptch intervals. Here, the mold oxide layer patterns 195 m the tWo-ptCil Intervals mean that two storage node contact plugs 185 are located between two adjacent mold oxide layer patterns 195, and the mold oxide layer patterns 195 In the one-ptch Intervals mean that one storage node contact plug 185 Is locc ted between two acllacent mold oxide layer patterns 195.

Ret'erTmg to FIGS. 6B and 7B, a conductive layer for the storage node electrodes, for example, a eloped polysihcon layer, Is deposited on the etch stoppers on which the mold oxide layer patterns 195 are Conned as shown in the first embodiment. The polyshcon layer is anisotropcally etched to form conductive spacers (not shown) of polyshcon on the both walls of the mold oxide layer patterns An msrlatmg layer Is deposited on the resultant structure and amsotropcally etched to form msulatng spacers (not shown) on the sidewalls of the conductive spacers. By repeatedly t'onnmg the conductive spacers and the msulatng spacers, the spaces between the mold oxide layer patterns 195 are filled Here, the conductive spacers contact the storage node contact plugs 185 and the last spacers are the nsulatmg' spacers The last spacers are formed on the etch stoppers 175 between the storage node contact phros 185 and the last spacers may have relatively larger brie wealth than the other insulating spacers. In the present embodmerZts, each of the spaces between the mold oxide layer patterns 195 Is filled by forming the conductive spacers four times and f'om m,, the insulating spacers four tunes, however, the widths and the numbers of the conductive spacers and the nsilatinO spacers can be control led.

I () The upper scrt'aces of the mold oxide layer patterns 195, the conductive spacers, and the nsrlatmg spacers are chemical mechanical pohslled to t'orm conductive brie patterns 261 and Insulating hne patterns 271 and 275 between mold oxide layer patterns 196. Here, reference numeral 196 denotes the mold oxide layer patients with plananzed upper surfaces The conductive hne patterns 261, which are the conductive spacers having planarzed upper surfaces, contact the storage node contact plugs 185 The nsulatmg line patterns 271 on the storage node contact plugs 185, which are the insulating spacers 220 having planarzed upper surt'aces, insulate the conductive line patterns 261 In addition, the Insulating hne patterns 275 fonned on the etch stoppers 175 insulate the conductive brie patterns 261 and separate the conductive hne patterns 261 In a direction parallel to the word hne structures 120 by one pitch, net, cell unit In the present Invention, four conductive one patterns 261 contact each of the storage node contact plugs 185 Referring to FIG. 6C, In order to del'ine the storage node electrodes In each cell, grooves 235 are formed by patternmO portions of the mold oxide layer patterns 196, the conductive line patterns 261, and the insulating Ih1e patterns 271 and 275 Here, the grooves 235 are t'omed to overlap the bit line structures 165 Accordingly, grooves 235 and the Insulating spacers 275 separate the conductive brie patterns 261 in Units oi'unt cell.

Rel'ernnO to FIGS. 6D and 8, an insulating layer for supporters Is deposited to sufficiently fill the grooves 235, and the insulating layer Is etched to a height smaller than the height of the conductive line patterns 261 so as to t'onm supporters 245 In some embodiments, the msulatrng layer filled m the grooves 235 is formed of an Insulating layer having an etching selectivity dit't'erent from the etching selectivties of the mold oxide layer patterns 196 and the nsulatmg brie patterns 271 and 275. Smce the supporters 245 cross through the contltictve line patterns 261, the supporters 245 separate the conductive hne patterns 261 according to cell. Frrtllernlore, the supporters 245 prevent the conductive line patterns 261 from lalUng or bending toward the adjacent contltctve One patterns 261. In addition, the supporters 245 are Donned to a height smaller than the height of the conductive Ime patterns 261 m order to secure storage node electrode capacitance Tllereat'ter, the mold oxide layer patterns 196 and the instlatng brie patterns 271 and 275 are removed by a conventional wet etching method lIere, since the mold oxide layer patterns 196 and the msulatmg One patterns 271 and 275 have an etching selectivity different Mom the etching selectivtres oftr1e etch stoppers 175 and the supporters 245, the mold oxide layer patterns 196 and the msclatng One patterns 271 and 275 are selectively removed. Thus, storage node electrodes 280 are completed The effects of the second embodiments can be the same as those of the first Bits Third Embodiments FIGS IDA through IOC are sectional views ot' stages in the manufacture of a semcontiactor memory device according to third embodiments of the present invention. 'the descriptions of the elements that are the same as the first and second embodiments will not be repeated, and the same reference numerals are allotted t'or the same elements of the first and second embodiments. In addition, the present embodiments include a method for f'onning storage node electrodes where the processes pert'ormed rip until l'onmng mold oxide layer patterns are the same as the ?5 processes ol'the t'irst embodnnents, thus the description will beam with the subsequent processes Referring to FIG. I()A, a first conductive layer 310 for storage node electrodes is f'onned on etch stoppers 175 on which mold oxide layer patterns 190 are conned.

I'hereat'ter, an nsulatmg layer 320 Is deposited on the Fret conductive layer 310.

3() rl'he first conductive layer 310 and the Insulating layer 320 are ansotroplcally etched to forth thirst conductive spacers 311 and insulating spacers 321 as shown In FIC. I OB A second conductive layer 330 for storage node electrodes Is deposited on the resultant structure. Here, the first conductive spacers 311 contact storage node contact plugs 185.

Next, by amsotropicalIy etehmg the second conductive layer 330, second conchictve spacers (not shown) are l'onned on the sidewalls of the Insulating spacers 321 1-lerc, the second conductive spacers contact the storage node contact plugs 185 while contacting, the sidewalls of the first conductive spacers 311. As shown In Fl(] 10C, the surface ot'the resultant structure Is chermcal mechanical polished to tong first conductive Inure Attends 317 formed ot'the first conductive spacers 311 and second concluctve Lee patterns 332 t'onnecl of the second concluctve spacers Here, tile fast conductive One patterns 312 are formed into an 1,-shape and portions of the second concluctve hne patterns 332 contact the lower portions of the first conductvc 1() line patterns 312. Thereat'ter, the msulatmg spacers 321 and the mold oxide layer patterns 130 are removed by a conventional wet etching method. Accordingly, storage node electrodes 300 formed of the first and second conduetve line patterns 312 and 332 are formed.

Here, the storage node electrodes 300 are fonned of two conductive Ime patterns; however, the widths and the numbers oJ'the conductive line patterns can be varied.

In addition, the mold oxide layer is formed to be parallel to the bit hnc structures no the present enbodiments; however, the mold oxide layer can be conned to be parallel to the word brie structures as shown In the second embodiments Fourth Embodiments FIG. 12A and 12B are the sectional views cut along lines C-C' of FIGS. I IA and I IB, respeetvely.

Tile clesengtons of the elements that are the same as the first through third embodiments will not be repeated, and the same reference numerals are allotted t'or the same elements of the first through third embodnner1ts. In addition, In the present embodiments, the processes pert'ormed up until forming storage node contact plugs are the same as the processes of the first through third embodiments, thus the descnptron will beam with the srbseqent processes.

3() Refemng to FIGS 11A and 12A, a mold oxide layer Is formed on storage node contact plugs 185 and etch stoppers 175 to a predetenmmed thickness. F1ere, tle mold oxide layer tor detennnnng the height ot'storage node electrodes can be formed to the desired height ot'the storage node electrodes. Thereafter, portions of the mold oxide layer are dry etched to t'om1 a plurality of mold oxide layer patterns 400 Here, the mold oxcle layer patterns 400 are fonmed in, for example, one-ptch Intervals, while teem, formed in the shape of waves Oil a plan view In other words, ridge portions ICE of the mold oxide layer patterns 400 located between the storage node contact plugs 185 anti valley portions X, of'the mold oxide layer patterns 400 are located on drain regions, which correspond to first contact pads 140a, or on an isolation layer IIO correspondm;, to the dran1 regions When conrlectmg the ncl;,e portions,Y' of the wave- shaped mold oxide layer patterns 400, straight lines are formed In addition, in some embodiments, tile stra,ht lines are parallel to bit Ones structures 165 I () As shown in FIGS I I B and 12B, a conductive layer 410 t'or storage node electrocles, tot- example, a eloped polysihcon layer, Is deposited on etch stoppers 175 on which the wave- shaped mold oxide layer patterns 400 are formed, and a but'fer nsulatm, layer 420 Is cleposted on the conductive layer 410 for storage node electrodes. 'I'lereat'ter, a chemical mechanical polishing is pert'orrned to expose the mold oxide layer patterns 400. Accordingly, the conductive layer 410 for storage node electrodes remains m a region det'ined by the mold oxide layer patterns 400.

Here, the sidewalls of the rermaimng conductive layer 410 for storage node electrodes have the same wave shape as the mold oxide layer patterns 400.

Next, as shown in FIGS. I I C and 13, grooves 430 are formed by dry etchm; , portions of the mold oxide layer patterns 400, the conductive layer 410 for storage node electrodes, and the insulating layer 420 in order to separate the storage node electrodes by cell Here, the grooves 430 are bonded between word line structures 120, on whcl1 drain regions (not shown) are t'onmed, while Bern;, perpendicular to the cKteidn= direction ot'the mold oxide layer patterns 400, i.e. the direction of bit hne structures It Is prel'erable that the grooves 430 pass tllrougil the valley portions,Y'of the mold oxide layer patterns 400.

Thereafter, as shown m If IGS 11 D and I 4, an msulatng layer for supporters is cleposted to suI'l'iciently fill the grooves 430. Here, the insulating layer t'or supporters can be t'omled of the same material as the etch stoppers 175, for example, a silicon 3() betide layer The nsulatmg layer Is wet or dry etched to a predetermined thickness so that the isolating layer Is remained In the grooves 430 to a height smaller than the height of the conductive layer 410 for storage node electrodes or the mold oxide layer patterns 400. Accordingly, supporters 440 are t'ormed.

The mold oracle layer patterns 400 and the msulatmg layer 420 are removed by a conventional wet etchmg method to t'onn storage node electrodes 425. fIere, since the etch stoppers 175 are Donned on the resultant structure on the semiconductor substrate 100 and the etching selectivity of the supporters 440 is clit'fercat from the etcl1n,, select\ sties of the mold oracle layer patterns 400 and the insulating layer 420, only the mold oxide layer patterns 400 and the insulating layer 420 are selectively rancor ed Thus, the storage node electrodes 425 are defined In units of each cell. In other words, the storage node electrodes 425 are separated m units ol'each cell by the supporters 440 In a direction parallel to the word hrles In addition, the supporters 440 I'onned In specific intervals support the storage node electrodes 425, which are Donned Into wave-shaped brie patterns. Theret'ore, the narrow and high storage node electrodes 425 are prevented from falling toward the adjacent storage node electrodes According to the present embodiments, since the storage node electrodes 425 are fanned In the wave shape, the surface area of the storage node electrodes 425 Increases. [n addition, since the storage node electrodes 425 are extended to the drain regions or the regions corrcspondrn,, to the drain regions, the surface area of the storage node electrodes 425 further increases.

Furthermore, since the supporters 440 are formed to separate the storage node electrodes 425 In umts of each cell, the storage node electrodes 425 are reduced or prevented l'rom l'allng or bending toward the adjacent storage node electrodes 425.

Here, the mold oxide layer patterns can be Conned by changing the intervals of the wave as shown in FIG. 15.

Referring to FIG 15, mold oxide layer patterns 450 are formed m the shape of waves m a plan view Mere, ridge portions X3 and valley portions X are formed to be located between storage node contact plugs 185. In this case, hoes formed by connecting the ridge portions Xi and lines t'onned by connecting the valley portions 4 are parallel with one another by a precletennmed distance, which is waler than th width ol'lhe active regions 3() If the wave shape ot'the mold oxide layer pattcnns 450 Is changed, the same effect Is attained In addition, as shown in FIG. 16, mold oxide layer patterns 500 may be fondled in two-ptch intervals In other words, the mold oxide layer patterns 500 are anran,ed in two-ptcl1 intervals as shown m the first embodiment while being t'ormed m the shape of waves on a plan view For example, m the mold oxide layer patterns 500, ridge portions BY; may be located between storage node contact plugs 185, and valley portions X' may be located on drain rcgons, r.e, first contact regions, or on an Isolation layer 110 corresponding to the drain regions If the mold oracle layer patterns 500 in two-pitch intervals are Conned, the same effect Is attained.

In aclchton, storage node electrodes 425 can be t'ormed by the method ptrt'onned no the third embodiments Flt'th Embodiments I () FIGS 17A and l 7B are plan views of stages n1 the menu t'acture of a semiconductor memory device according to cloth embodiments of the present invention The processes performed up until fondling etch stoppers 175 are the same as the processes of the Fret and second embodiments, thus the descnpton Will begin with the subsequent processes Referring to FIGS. 17A, mold oxide layer patterns 600 are t'ormed m the shape of waves m a plan view, on etch stoppers 175. Here, the mold oxide layer patter-es 600 can he formed In, for example, one-pitch intervals. In other words, lines Donned by connecting ridge portions Xs or valley portions X of the mold oxide layer patterns 600 arc substar1trally parallel to word lme structures 120. In addition, the mold oxide 2() layer patten1s 600 are t'orrned to expose each of the storage node contact plugs 185 between the adjacent mold oxide layer patterns 600 on the same hues The mold oxide layer patterns 600 are fonmed on regions without storage node contact plugs, e, on dram regions and on an Isolation layer 110 corresponding to the drain regions.

A plurality of conductive brie patterns 610 and insulating lme patterns 620 are alternately t'ormed between the mold oxide layer patterns 600. Here, the plurality of conclrctve line patten1s 610 and n1stilatn:, One patterns 620 are formed mto waves according to the wave-shaped mold oxide layer patterns 600. In this case, the conclcctve One patterns 610 and the nstlatmg lme patterns 620 are formed by the above-descnbed methods.

As shown in FIG. 17B, portions of the mold oxide layer patterns 600, the conductive Ime patterns 610, and the msulatrng hne patterns 62() are etched to form grooves 630 'I'he grooves 630 are formed on regions, which overlap bit One structures 16S, m order to separate the conductive One patterns 610 in units of each cell Here, the conductive line patterns 610 are defined In units of each cell by the grooves 630 and the mold oxide layer pattern 600, and the concluctve hoc patterns 610 are formed mto waves while contacting, the storage node contact plugs 185.

Thereafter, supporters (not shown) are formed m the grooves 630 by the abcve-descubed method. The mold oxide layer patterns 600 and the msulatng hne patterns 620 are etched to forth storage node electrodes 625.

[I' the mold oxide layer patterns 600 are formed to be parallel to the word One structures 120, the same effect may be attained.

As shown In FIG. IS, the same cEt'ect may be attained by f'ormm, the mold oxide layer patters 700 Into waves In two-ptch Intervals.

I () As described above, according to embodiments of the present invention, storage node electrodes are f'ormecl In a plurahty of One pattern types havmg a fine brie widtl1. Thus, the surface area of the storage node electrodes can increase In adclton, the supporters Corned of an insulating layer are formed to be perpendicular to the extending direction of the brie patterns of the storage node electrodes.

Theret'ore, the supporters separate the storage node electrodes m units of each cell, and the supporters support the storage node electrodes, thereby reducing or preventing the storage node electrodes t'rom falling or bending toward the adjacent storage node electrodes.

Furthermore, the regions for t'omng the storage node electrodes may be increased so that the surt'ace area of the storage node electrodes may be increased.

While this invention has been particularly shown and described with reference to preferred embodiments thercol; it will be understood by those skilled In the art that various changes m form and cletals may be made therein without departing from the spit it and scope of the invention as defined by the appended claims.

In the drawimys and specification, there have been disclosed typical preferred embodiments of the n1venton and, although specific temls are employed, they are Sect In a generic and descriptive sense only and not for purposes of limitation, the scope ot'the mventon bemg set forth n1 the following claims.

Claims

CLAIMS: I storage node for a semconduetor memory device comprsmg a

plurality of treestan:1n, storage node electrodes that project away from a semiconductor memory substrate by a first clstance; and a supporter that Is configured to support at least one of the teestanding storage node electrodes and that projects away from the semiconductor memory substrate by a second distance that Is less than the first distance
2 A storage node accordm;, to Claim 67 wherem the plurality of 1 () freestanding storage nodes extend along two spaced apart rows and wherein the supporter extends between the two spaced apart rows
3. A method of fabricating a storage node for a semiconductor memory device comprising: fondling a plcraUty of freestanding storage node electrodes that project away Tom a semconcluctor memory substrate by a first distance; and fornrnO a supporter that is contgcred to support at least one of the freestanding storage node electrodes and that projects away from the semiconductor memory substrate by a second distance that is less than the first distance.
4. A method accordm;, to Claim 3 wherein the plurality of freestanding storage nodes extend along two spaced apart rows and wherein the supporter extends between the two spaced apart rows.