GB2410374A

GB2410374A - DRAM storage electrode manufacturing method

Info

Publication number: GB2410374A
Application number: GB0500293A
Authority: GB
Inventors: Byung-Jun Park
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2002-06-27
Filing date: 2003-06-24
Publication date: 2005-07-27
Anticipated expiration: 2023-06-24
Also published as: GB2410376B; GB0500295D0; GB0500291D0; GB2410376A; GB2410373A; GB0500293D0; GB2410375B; GB2410373B; GB0500294D0; GB2410375A; GB2410372A; GB0500290D0; GB2410372B; GB2410374B

Abstract

Conductive 261 and insulating 271 line patterns are formed in a mould oxide pattern 196 to form vertical fins of a DRAM capacitor electrode. Adjacent capacitors are separated by a groove etched into the conductive and insulating line patterns. A portion of the mold oxide layer (245) is not removed from between adjacent capacitors to provide support to the vertical fins of the device (see figure 8).

Description

24 1 0374 SEMICONDUCTOR MF,MORY DF,VICES AND METHODS FOR MANUFACTURING,

TIIE SAME, USING SIDF,WALL SPACF,RS

Field of the Invention

I'he present mventon relates to semiconductor memory devices and methods for manufacturulg the same, and more particularly to storage nodes for semiconductor memory dcvces and methods t'or manufacturing the same.

Background of the invention

As semiconductor memory devices have become highly integrated, the areas of unit cells and the distances between cells may be reduced. However, capacitors lavmg a large capacitance within small areas are desired, to provide predetermined ] 0 capacitances. As Is well known to those having skill no the art, semiconductor memory crevice capacitors include a lower electrode, also referred to as a storage node electrode, an upper electrode, also rel'erred lo as a plate electrode, and a dielectric layer therebetween. Conventional methods for securing large capacitances of the capacitors include usmg a lugl1 dielectric material as the dielectric layer, reducing the thickness of'a dielectric layer, and/or increasing the surface area of storage node electrodes of'the capacitors.

A method for increasing the surface area of the storage node electrodes includes l-'rnnng tin-ee-dnensonal storage node electrodes, for example, cylindrical or concave electrodes.

9() 1-1( 1 Is a sectional view 11ustratmg conventional concave storage node electrodes Refcrrhg lo FIG. 1, an intericvel Insulating layer 12 is tombed on a semiconductor substrate I0 havhig circuit devices (not shown), such as MOS transistors. The mtcrlevel Insulating layer 12 includes storage node contact plugs 14 2: that are widely known lo connect a source region (not shown) ova selected MOS transistor with storage node electrodes 16, which will be t'omied h1 a subsequent process. 'I'hcreat'ter, the cup-silapcd concave storage node electrodes 16 are formed on the prcdetennmed portions ol'the storage node contact plugs 14 and the interievel Stun layer 12. A method t'or looming the concave storage node electrodes 16 Is A) as t'ollows First, a mold oxide layer (not shown) having a predctennined thickness is deposited on the interievel Insulating layer 12 including, the storage node contact plugs 14. 'l''lc nold oxide layer Is etched Into hole shapes until exposing the storage node contact pings 14, thereby def ning a region for forming the storage node cicctrodes Thereafter, a conductive layer (not shown) and a node Isolation insulating layer (not shown) are subsequently formed on the mold oxide layer so as to contact the exposed storage node contact plugs 14. 'file conductive layer and the node Isolation nsulatng layer are chemical mechanical polished to expose the surface of the nold oxdc layer. Thercaftcr, the node isolation insulating layer and the mold oxdc layer arc removed by a conventional method so that the concave storage node I () electrodes 16 are t'ormed.

I lowever, the concave storage node electrodes formed by the abovedescribed Acted may have the following problems.

In order to nanufacturc the storage node electrodes having large capacitance, talc height ol'lhe storage node electrodes may need to be increased withy a limited ar ca In addition, in order to increase the hcgilt of the storage node electrodes, the thickness ol'thc mold oxide layer may need to be increased. In this case, when the Nolan oxdc layer is etched to define the region t'or forming the storage node electrodes, a large slope may occur on the sidewalls of the holes, and the critical dnension of the exposed storage node contact holes may be reduced. Accordingly, 9() the lower portions ol'the thin and high storage node electrodes may become narrower so trial the storage node electrodes may become unstable. In addition, the distance between adjacent storage node electrodes may be reduced so that it may be difficult to provide msulaton between the storage node electrodes.

Frrthcnnore, due to thermal stress generated in subsequent processes, some of' the weak storage notle electrodes may fall or break and generate bridges between unit storage node electrodes, thereby causmg defects in the device.

Summary of the Invention

An aspect of tile present invention provides a semiconductor memory device compnsm;, a scmconcluctor substrate, an ntericvel insulating layer on the senucontiuctor substrate, storage node contact plugs in the intcrlevel insulating layer, and stora,c node electrodes, which comprise a plurality of conductive line patterns separated m prcdeterrinncd intervals while having, a predetermined height, contacting the sloray,c node contact plugs, wherein, the storage node electrodes are separated by insulating One patterns between selected storage node electrodes in units of a unit cell of the memory dcvce.

Another aspect of the present invention provides a semiconductor memory device conprsmg an nterlevel insulating layer on a semcontiuctor substrate mcludnig a plurality ol active regions, a pluraLty of word line structures passing over the active regions, source and drain regions on the active regions at respective sides of the word line structures, and a plurality of bit hne structures crossing the word Ime structures, elcctrcally connecting to the drain regions, and passing between the active rcgons; etch stoppers on the mterlevel insulating layer; storage node contact plugs I () loaned no the ntcrlevel Insulating layer and the etch stoppers; storage node electrodes, which comprise a plurality of conductive line patterns separated in predetennned intervals while having a predetermined height, contacting to the storage node contact plugs, and supporters between the storage node electrodes and cxiendng perpcudcular to an extending direction ol the line patterns ofthe storage node electrodes h1 these cmbodhilcnts, the plurality of line patterns are formed into straight Ones.

Another aspect of the present invention provides a semiconductor memory device comprising an interlevel insulating layer on a semiconductor substrate Including a plurality of active regions, a plurality of word One structures passing over ?() tile active regions, source and dram regions on the active regions at respective sides of the word Imc structures, and a plurality of bit line structures crossing the word line structures, electrically connccthig to the drain regions, and passing between the active regions; etch stoppers on the hiterlevel Insulating layer; storage node contact plugs in the ntericvel Insulating layer and the etch stoppers; storage node electrodes, which comprise a plurality of conductive hue patterns separated in the same intervals while having a specific height, contacting the storage node contact plugs; and supporters between (he storage node electrodes while being perpendicular to an extending dircclon of the Idle patterns of the storage node electrodes. In these embodiments, the plurahty of line patterns are formed in the shape of waves m a plan view.

3() In another aspect of the present invention, there are provided methods of manrlacturng a semiconductor memory device In these methods, an mterlevel insulating layer- is deposited on a semiconductor substrate, and a plurality of storage node contact plugs are longed In the nterievel Insulating layer m specific intervals.

I hereafter, mold oxide layer patterns are for-mea on the interlevel Insulating layer In specific intervals to expose the storage node contact plugs, and the spaces between the nod oxide layer patterns are l'illed by alternately forming conductive line patterns and nsulatmg line patterns, repeatedly, on the sidewalls of the mold oxide layer pattems. Grooves arc fonned perpendicular to the mold oxide layer patterns by etching portions of the mold oxide layer patterns, the conductive line patterns, and the Slating hue pattems. Storage node electrodes are l'onmed by selectively removing the mold oxide layer patterns and the insulating line pattems.

In a yet l'urtller aspect of the present nventon, there arc provided methods for nanul'actunng a semiconductor Sensory device. In these methods, a semiconductor 1 () substrate, which includes a plurality of active regions, a plurality ol'word line structures passing, over the active regions, source and drain regions formed on the aC(IVC regions at respective sides of the word line structures, and a plurality orbit Ime structures crossing the word line structures, electrically connecting to the drain regions, and passing between the active regions, is prepared. An interlevel insulating layer Is conned on the scmconductor substrate, etch stoppers are formed on the nterlcvel msulathlg layer, and storage node contact plugs arc formed In the interlevel hsulatulg layer and the etch stoppers at specific intervals. Thereafter, a plurality of mold oxdc layer patterns are formed on the etch stoppers at specific intervals to expose the storage node contact plugs. The spaces between the mold oxide layer 9() patrons are ('illed by alternately l'onnng at least one conductive line pattern and hlsulathg brie pattern on the sidewalls of the mold oxide layer patterns In order to follow the shape of the mold oxide layer patterns. Grooves are formed perpendicular to the mold oxide layer patterns by etching portions of the mold oxide layer patterns, the conductive lhc patterns, and the hlsulatng line pattems. Thereafter, supporters arc 1'onneci us the grooves, and storage node electrodes are fonmed by selectively rcnovng the mold oxide layer patterns and the hlsulatng line patterns. In these cnbodmlents, the mold oxide layer patterns extend into straight lines and the mold oxide layer patterns and the supporters separate the storage node electrodes In units of each ceil.

3() In a still other aspect ot'the present invention, there are provided methods for nanutacturng a semiconductor memory device. In these methods, a semiconductor substrate, which includes a plurality of active regions, a plurality of word line structures passmg over the active regions, source and drain regions formed on the active regions at respective sides of the word hne structures, and a plurality of bit hne strctrres crossing the word line structures, electrically connecting to the drain reg,ons, and passing between the active regions, Is prepared. An interlevel insulating layer Is l'onned on the semiconductor substrate, and etch stoppers are formed on the ntcricvcl ms'latmg layer. Thereafter, storage node contact plugs are formed n1 the mtcrievel nsrlatmg layer and the etch stoppers at specific intervals, and a plurality of mold oxide layer pattems, which are formed in the shape of waves on a plan view, are ['onnetl on the etch stoppers to expose the storage node contact plugs. The spaces between the mold oxide layer patterns are filled by alternately forming at least one contirctve Ike pattern and insulating One patten1 on the sidewalls of the mold oxide I () layer patterns hi order to follow the shape of the mold oxide layer pattems.

I'hereaf'ter, Hooves are t'oned perpendicular to the mold oxide layer patterns by etching portions of the mold oxide layer patterns, the conductive line patterns, and the msulatmg Idle patterns. Supporters are formed n1 the grooves, and storage node electrodes are formed by selectively removing the mold oxide layer patterns and the hisrlatnig Ime pattems. In these embodiments, the mold oxide layer patterns and the supporters separate the storage node electrodes in units ot'each cell.

Another aspect of the present invention provides a storage node. for a scnllcolldcctor memory device which includes a pair of spaced apart mold oxide layer patters on a sclicontirctor memory device substrate that defines facing mold oxide 2() layer patter, sidewalls. A pair of first conductive spacers are provided, a respective one of w}ucl1 is on a respective one of the facing mold oxide layer pattern sidewalls and face one another A pair of first insulating spacer is provided, a respective one of which Is on a respective one ol'the pair of first conductive spacers, opposite the respective one of the lacmg mold oxide layer pattern sidewalls. A pair of' second conductive spacers Is provided, a respective one of which is on a respective one of tile pair of first insulating spacers, opposite the respective one of the pair of first conductive spacers. At least one second insulating spacer is provided between the pair of second contiuctivc spacers. in some embodiments, a single insulating spacer extcHtis between the pair of'second conductive spacers.

3() .itora,,c notice may be fabricated according to some cmbodncnts of the present nventon by forming spaced apart mold oxide layer patterns on a scmconductor memory device substrate that define facing mold oxide layer pattern sidewalls A first conductive spacer is foamed on each of the facing mold oxide layer Patton sidewalls. A first insulating spacer Is fonned on each of the first conductive spacers A second conductive spacer is fonned on each of the first insulating spacers and at least a second nsulatmg spacer is formed on the second conductive spacers. In some embodiments, the first conductive spacers, the first insulating spacers and the second conductive spacers are f'onned by confomially looming a conductive or insulating layer on the facing mold oxide layer patter, sidewalls and on the semiconductor memory device substrate thereUctwecn, and then anisotropically caching the conductive or insulathg layer lo remove at least some the layer that is on the senconcinctor memory device substrate therebetween.

In other cmboddilents of the invention, a storage node for a semiconductor I () ncmory device includes a plurahty of freestandhg storage node electrodes that project away from a semiconductor memory device substrate by a first distance. A supporter Is conl'igured to support at least one of the freestanding storage node electrodes and projects away from the semiconductor memory substrate by a second distance that is less than the first distance. In other embodiments, the plurality of I'recstandng storage nodes extend along two spaced apart rows, and the supporter extends between the two spaced apart rows. Storage nodes may be fabricated by ironing the freestandhig storage node electrodes and then conning the supporter to support at least one of the l'reestanding storage node electrodes.

2() Brief Description of the Drawines

FIG. I Is a sectional view illustrating a conventional semiconductor memory device haVmg concave storage node electrodes; FIGS 2A through 2D are plan views of stages u1 the manufacture of a semiconductor memory device according to f rst embodiments of the present invention; FlCiS. 3A through 3C are sectional views of stages in the manufacture of a semiconductor memory device according to the first embodiments ol'the present mventon, 1 1(-, 4 Is a perspective view Ihstrating a semiconductor memory device 3() according to the f rst ernbodunents of the present hventon; FTC: . 5 Is a plan view illustrating a modified semiconductor memory device according to the f rst embodiments of the present mventon; FIGS. ('A through 6D are plan views of stages in the manufacture of a semiconductor memory device aceordmg to second embodiments of the present Anton, I-;IGS 7A and 73 are sectional views of stages in the manufacture of a semiconductor memory device according to the second embodiments ofthe present invention, FIG. 8 Is a perspective view illustrating a semiconductor memory device according, to the second embodiments of the present invention; FIG 9 Is a plan view illustrating a modified semiconductor memory device I () accords to the second embodiments of the present invention; FIGS. I ()A througl1 1 ()C are sectional views ol stages in the manufacture of a semiconductor memory device according to third embodiments of the present veto'; FIGS. I I A through I 1 D are plan views of stages in the manufacture of a senconcluctor memory device according to fourth embodiments of the present invention; F l( iS 1 2A and 1 2B are sectional views of stages in the manufacture of a semicontinctor memory device according to the fourth embodiments of the present it; 2() FIGS. 13 and 14 are perspective views '11ustrating a semiconductor memory device according to the fourth embodiments of the present invention; FIG. 15 is a plan view illustrating a modified semiconductor memory devree accorduly to the fourth embodiments of the present invention; FIG I (I Is a plan view illustrating another modified semiconductor memory device according to the fourth embodiments of the present invention; FIGS I 7A and 1 7B are plan views of stages in the manufacture of a senicontinclomenory device accorcimg to fifth embodiments of the present mventon; and 1 1(:] 18 Is a plan view Illustrating a modified semiconductor memory device A) according to the filth embodiments of the present invention.

Detailed Description

I he present mventon now will be described more fully hereinafter with reference to the accompanying drawings, In which embodiments of the mventon are shown. However, this Invention should not be construed as limited to the cmbodimenis set foril1 herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope ofthe nvenlon lo those skilled n1 the art. In the drawings, the thickness of layers and rcgons arc exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element such as a layer, region or substrate is rcf'cn-ed to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other clement or intervening elements may also be present.

In contrast, when an element is referred to as being "directly on" or extending I () "directly onto" another element, there are no intervening elements present.

First Embodiments Reterring to FIGS. 2A and 3A, an Isolation layer 110 is formed In a selected region ot'a semiconductor substrate 100 by a conventional STI method, thereby dclning active regions 115 on which devices will be formed. Here, the semiconductor substrate 100 may be a silicon substrate including P-type or N-type mipuntes and nay include wells n1 a predetermined region to forth a device. The active rcgIons 1 15, t'onncd In, for example, a bar shape, are spaced apart by a predetenilmed distance in rows and columns. Here, the active regions 115 are 0() arranged to allernalc by each row. 1n other words, the spaces between the adjacent active regions 115 correspond to the central portions ofthe active regions ofthe sutseclucnt row h1 the direction ofthc longer axis ofthe active regions 115. Here, the central portions of the active regions will be drain regions.

l'hcrcafter, word hnc structures 120 are conned on the semiconductor substrate 100. Here, the word line structures 120 are extended to be parallel with one anotlcr while berm, perpendicular to the longer axis of the active regions 115. In addition, a pair of word line structures 120 may be arranged for each of the active regions 115. Source and dran1 regions (not shown) are formed in the active regions at both sides of tile word line structures 120 by a conventional method.

3() A first mtericvel msulatul layer 130 Is Combed on the semiconductor substrate havn1g the word hue structures 120 and on the source and drain regions. First and second contact pads 140a and 140b, which contact the source and drain regions winkle havmg the same heigl1t as the first interlevcl insulating layer 130, are Donned in flee first mterlevel n1sulatmg layer 130. A method for f'onning the first and second contact pads 140a and 140b will now be described. After the first nterlevel nsulating layer 130 is formed, the first interlevel insulath1g layer 130 is etched to expose il1e source and drain regions. A conductive layer, for example, a doped polyslcon layer, Is depositeti to contact the exposed source and drain regions, and the conductive layer Is etched back or chemical mechanical polished so as to expose the surface of the first hiterlevel Insulating layer 130 Accordingly, the first and second contact pads 140a and 140b are formed. Here, the fust and second contact pads 140a and 140b contact the drain region and the source regions, respectively A second nterlevel insulating layer 150 is formed on the first interlevel 1() nsulatng layer 130 and bit Idle structures 165 are fonned on the second interievel Insulating layer lSO. Here, the bit brie structure 165 includes a bit fine 160, a mask layer 162 bombed on tile bit line 160, and spacers 164 Conned on both walls of the bit line 160 and the mask layer 162. The mask layers 162 and the spacers 164, formed of, for example, silicon nitride layers, are fonned to surround the bit lines 160 in order to form seif:algned contact holes when forming storage node contact holes. Tn adtition, n1 some embodinents, the bit line structures 165 are fonned to be perpendicular to the word hne stnchres 120 and that the bit line structures 165 are arranged on the isolation layer 110 between the active regions 115 while ben1g parallel to the longer axis of the active regions. I lore, though not shown in the ?() drawulys' bit Idle contact plugs for connecting the first contact pads 140a and the bit One structures 165 are formed h1 the second interlevel insulating layer 150 by a conventional method, before l'omling the bit line structures 165.

A third interlevel nsulatmg layer 170 and etch stoppers 175 are sequentially I'on1leti on the second niterlevel msulathig layer 150 havmg the bit fine structures 165.

filers, the first through third interlevel insulating layers 130,150, and 170 maybe l'orncd ol; for example, n1sulatng layers ofthe silicon oxide layer group. The etch stoppers 175 are l'orrned of Insulating layers, for example, silicon nitride layers, havug an etching selectivity different frown the etching selectivities of the second and thud nterlevel n1sulatulg layers 150 and 170. The etch stoppers 175, the third 3() nterlevel usulatug layer 170, and the second mterlevel insulating layer 150 are etched to expose the second contact pads 140b, which contact the source regions, so that storage notic contact holes 180 are formed Here, the storage node contact holes are formed by a scif-aligning method using the bit hue structures 165 Thereafter, a conductive layer, for- example, a doped polysilicon layer, Is deposited to sufficiently Iill the storage node contact holes 180, and the doped polysilicon layer is chemical mechanical polished to expose the etch stoppers 175. Accordingly, storage node contact plugs 185 are formed Other conventional techniques for fonmmg a scmconduclor memory device substrate may be used.

A mold oxide layer Is formed on the storage node contact plugs 185 and the etch stoppers 175 to a predetermined thickness. In some embodiments, the mold oxide layer for detennhnig the height of the storage node electrodes Is formed to a hcght higiler than the desired height of the storage node electrodes by a predctermmed heigilt, considering that the mold oxide layer will be chemical mecilamcal poUsiled to the predetermined height n1 the present embodiments. The mold oxide layer is etched to overlap the bit line structures 165 so that mold oxide layer patterns 190 arc formed. Here, the mold oxide layer patterns 190 can be fanned no predetenmned nitcrvals, for example, one-pitch or two-pitch. The mold oxide layer patlens 190 of FIG. 2A are arranged in two-pitch intervals and the mold oxide layer patterns 190 ot FIG 5 are arranged in one-pitch intervals. In this respect, the mold oxalic layer patterns 190 in the two-pitch intervals mean that two storage node contact plugs 185 are located between two adjacent mold oxide layer patterns 190. In addition, the line width of the mold oxide layer patterns 190 may be equal to or less than the hue width of the bit line structures 165.

2() Referrhg to FIG. 3B, a conductive layer for the storage node electrodes, tor example, a polysiDcon layer, is deposited on the etch stoppers 175 on which the mold oxide layer patterns 190 are formed. Next, the polysilicon layer is anisotropically etched to form conductive spacers 200 of polysilicon on both walls of the mold oxide layer patterns 190. An insulating layer is deposited on the resultant structure and anisotropcally etched to foml uisulatulg spacers 220 on the sidewalls of the COntlLICtI\C specters 200. By repeatedly fonnhg the conductive spacers 200 and the nsrlatmg spacers 220, the spaces between the mold oxide layer patterns 190 are f fled. Here, in order to separate unit ceils, the last spacers Donned between the mold oxide layer patterns 190, he., the spacers fonmed at the center points between the mold 3() oxdc layer patrons 190, arc the insulating spacers 220. In addition, the conductive spacers 200 are formed to contact the node contact plugs 185. In the present cmbodmicnts, the spaces between the mold oxide layer patterns 190 are filled by lormng the conductive spacers 200 twice and Donning the insulating spacers 220 twice; however, the widths and the numbers of the conductive spacers 200 and the insulating spacers 220 can be varied.

Refcn-mg to FIGS. 2B and 3(:', the upper surl'aces of the mold oxide layer patterns 190, the conductive spacers 200, and the insulating spacers 220 arc chemical mccilamcal polished to planarize the upper surfaces so that conductive line patterns 201 and n1sulatng line patterns 221 and 225 are formed between mold oxide layer patters 191 Here, reference numeral 191 denotes the mold oxide laycrpatten1s having plananzed upper surfaces. And, the conductive line patterns 201 are the conductive spacers 220 having plananzed upper surfaces, and the insulating line I () patterns 221 and 225 are the Insulating spacers 220 having planarizcd upper surfaces.

I'he conductive line patterns 201 respectively contact the storage node contact plugs 18S and the insulathig hne patterns 221 and 225 insulate the conductive line patterns 201 In particular, the insulating, line patterns 225 fanned on the etch stoppers 175 separate the conductive line patterns 201 by one pitch, i.e., the size of unit cells, in a Erection parallel to the bit line structures 165 while insulating the conductive tine patterns 201. In the present embodiments, each ofthe storage node contact plugs 185 Includes, t'or example, two conductive line patterns 201 and one Insulating line pattern 221 therebetween.

Rct'cn-ng to FIG. 2C, n1 order to define the storage node electrodes, grooves 2() 230 are fonned by patterning portions of the mold oxide layer patterns 191, the conductive hnc patterns 201, and the insulating line patterns 221 and 225. Here, the grooves 230 extend to be perpendicular to the extending direction of the mold oxide layer patterns 191, '.e., to be parallel to the word fine structures 120. The grooves 230 are formed between the word line structures 120 on which the drain regions are lornecl no order to secure maximum storage node electrode regions. In other words, a couple ol'word lines 120 are arranged between a couple of adjacent grooves 230 such that the grooves 230 open the etch stoppers 175.

Referring to FIGS. 2D and 4, an insulating layer for supporters Is cieposited to sufficiently bury the grooves 230, and the insulating layer is etched to a height smaller A) than the height ol'tile conductive lute patterns 201 so as to Tome supporters 240. Here, the nsulatn, layer for supporters Is romped of an Insulating layer having an etching selcctvty cl'l'I'erent From the etchmg selectivities of the mold oxide layer patterns 191 and to msulatul One patterns 221 and 225. Accordingly, the insulating layer Is wet etched to Iowa the supporters 240.

Since the supporters 240 are fonncd m the grooves 230, the supporters 240 cross through the conductive line patterns 201 so that the supporters 240 separate the conductive hne patterns 201 according to cell. Furthermore, the supporters 240 support the conductive lice patterns 201, thereby reducing or preventing the conductive hne patterns 201 fiom falihig or bending toward the adjacent conductive line patterns 201. In addition, the supporters 240 have a height smaller than the height of the conductive brie patterns 201 in order to secure storage node electrode capacitance. Therealler, the mold oxide layer patterns 191 and the insulating hne

patterns 1 () 221 and 225 arc removed by a conventional wet etchmg mctilod. Here, since the mokl oxide layer patterns 191 and the insulating line patterns 221 and 225 have the ciclug sclectvity do l'lcrent fiom the etching selectivities of the etch stoppers 175 and the supporters 241), the mold oxide layer patterns 191 and the insulating hne patterns 221 and 225 are selcctvely removed. Thus, the storage node electrodes 250 formed ol'the plurality of conductive line patterns 201 are completely formed.

The storage node electrodes 250 according, to the present embodiment are Conned of a plurality of conductive line patterns 201 having a fine line width so as to increase the surl'acc area of the storage node electrodes 250. In addition. the supporters 240 separate and support the storage node electrodes 250 according to cell 9() So as to reduce or prevent the storage node electrodes 250 from falling or bendmg toward the adjacent storage node electrodes 250. Furthermore, as shown m FIG. 2D, the storage node electrodes 250 are extended to the regions corresponding to the drain regions (not shown) as well as the regions having the bit line structures 165 so as to iicrcase the surface area of the storage node electrodes 250.

Siecond Embodlnlcllts Ref'en-'rig to FIGS. (jA and 7A, an Isolation layer 110 is 1'onmed on a semiconductor substrate 100 as shown in the first embodiment to define active regions 115. Word 3() line structures 120 are l'omed on the semiconductor substrate 100 as follows. Al'ter subsequently depositing a gate insulating layer 121, word lines 123, and a hard mask layer 125, the layers are patterned to be pcrpendcular to the longer axis of the active regions 115. Word line spacers 127 arc formed on the sidewalls of the patterned hard mask layers 125 and word Imes 123 by a conventional method to form the word hne stnctrcs 120 Here, the hard mask layers 125 and the word line spacers 127 are formed of silicon nitride layers having an etching selectivity different from the etching sclectvty of'an mtcr-level msulathl layer of a silicon oxide layer group, which will be f'orrilcd to 1'onn self-ahyning contact holes in a subsequent process. In addition, the word hue strctres 120 extend so as to be parallel with one another and a couple of word hne structures 120 are arranged on each active region 11S. Source and drain regions (not shown), a first interlevel hisulating layer 130, contact pads 140a and 140b, a second interlevel insulating layer 170, etch stoppers 175, and storage node contact pads 185 are romped in the active regions 115 at both sides ol'the 1() word fine structures 120 by the method illustrated in the first embodiment.

A mold oxide layer Is formed on the storage node contact plugs 185 and the etch stoppers 175 to a predetermined thickness. As described above, the mold oxide l,iycr for determining the height of the storage node electrodes is formed to a height higher than the fleshed height oi'the storage node electrodes by a predetermined hegilt '1'hc portion ol'the mold oxide layer is etched to expose the storage node contact plugs 185, thereby forming mold oxide layer patterns 195. In the present embocinnents, the mold oxide layer patterns 195 are arranged to be parallel to the word lhic structures 120 while overlapping the drain regions of the active regions 115.

In addition, the mold oxide layer patterns 195 can be formed in predetermined 2() intervals, for example, one-pitcl1 or two-pitch. The mold oxide layer patterns 195 of lo I(i. 6A are arranged n1 two-ptch intervals, and the mold oxide layer patterns 195 of FIG. 9 are arranged in one-pitch intervals. Here, the mold oxide layer patterns 195 in the two-ptch intervals mean that two storage node contact plugs 185 are located between two adjacent mold oxide layer patterns 195, and the mold oxide layer patrons 195 in the one-pitch intervals mean that one storage node contact plug 185 Is located between two adjacent mold oxide layer patterns 195.

Refcrr-ng to FIGS. 6B and 7B, a conductive layer for the storage node clecirodes, for example, a doped polysilicon layer, is deposited on the etch stoppers 17S on which the mold oxide layer patterns 195 are lammed as shown In the first 3() enbodnenl. 'l'he polysihcon layer Is ansotropcally etched to forth conductive spacers (not shown) ol'polysilicon on the both walls of the mold oxide layer patterns 195. An uisulatng layer is deposited on the resultant structure and anisotropcally etched to l'oml insulating spacers (not shown) on the sidewalls of the conductive spacers. By repeatedly conning the conductive spacers and the insulating spacers, the spaces between the mold oxide layer patterns 195 are filled. Here, the conductive spacers contact the storage node contact plugs 185 and the last spacers are the mslathig spacers. The last spacers are longed on the etch stoppers 175 between the storage node contact plugs 185 and the last spacers may have relatively larger fine S width than the other nsulatulg spacers. In the present embodiments, each of the spaces between the mold oxide layer patterns 195 is filled by Conning the conductive spacers four times and forming the insulating spacers four times; however, the widths and the numbers ol the conductive spacers and the insulating spacers can be controlled.

I () The upper surfaces of the mold oxide layer patterns 195, the conductive spacers, and the msulatmg spacers are chemical mechanical polished to form contt'ctve One patrons 261 and insulating One patterns 271 and 275 between mold oxide layer patterns 196. Here, reference numeral 196 denotes the mold oxide layer patterns with plananzed upper surfaces. The conductive line patterns 261, which are the conductive spacers having planarized upper surfaces, contact the storage node contact plugs 185. The hsulatmg hne patterns 271 on the storage node contact plugs 185, which are the nsulathg spacers 220 having planarized upper surfaces, insulate the conductive hne patterns 261. In addition, the insulating line patterns 275 Donned on the etch stoppers 175 insulate the conductive line patterns 261 and separate the 2() conductive Ike patterns 261 In a direction parallel to the word line structures 120 by one pitch, net, ceil unit. In the present invention, four conductive line patterns 261 contact each ol the storage node contact plugs 185.

RcLerThig to FIG. 6C, in order to define the storage node electrodes in each cell, grooves 235 are Donned by patterning portions of the mold oxide layer patterns 196, the conductive line patterns 261, and the insulating line patterns 271 and 275.

Here, the grooves 235 are tonged to overlap the bit line structures 165. Accordingly, grooves 235 and tle msulatnig spacers 275 separate the conductive line patterns 261 he units of unit cell.

Refcn-mg to FIGS. 6D and 8, an insulating layer for supporters is deposited to 3() s.lficently f ll the grooves 235, and the insulating layer is etched to a height smaller than the height of the conductive Ime patterns 261 so as to form supporters 245. In sonic embodiments, the uisulatulg layer filled m the grooves 235 is formed of an nsulatmg layer navmg an etching selectivity different from the etching selectvtes of the mold oxide layer patterns 196 and the hisulating hne patterns 271 and 275. Since the supporters 245 cross through the conductive line patterns 261, the supporters 245 separate the conductive line patterns 261 according to ceil. Furthermore, the supporters 245 prevent the conductive fine patterns 261 from falling or bending toward the adjacent conductive hne patterns 261. In addition, the supporters 245 are I'ormecl to a Hewitt smaller than the height of the conductive line patterns 261 in order to secure storage node electrode capacitance.

['hereafter, the mold oxide layer patterns 196 and the Insulating line patterns 271 and 275 are removed by a conventional wet etching method. Here, since the mold oxide layer patterns 196 and the insulating line patterns 271 and 275 have an () etclng sclectvty d'I'fcrent {Tom the etching selectivities of the etch stoppers 175 and the supporters 245, the molci oxdc layer patterns 196 and the insulating Ih1e patterns 271 and 275 are selectively removed. Thus, storage node electrodes 280 are completccl.

The cff'ccts of the second embodiments can be the same as those of the first embodhnents.

I'llnd Embodiments FIGS. I OA through 10C are sectional views of stages in the manufacture of a semiconductor memory device according to third embodiments of the present 2() invention. The descnptons ol'the elements that are the same as the first and second cmbodunents will not be repeated, and the same ret'crence numerals are allotted for the same elements oI'the first and second embodiments. In addition, the present cmboduncuts n1cludc a method for forming storage node electrodes where the processes performed up until fomling mold oxide layer patterns are the same as the processes of tile first embodiments, thus the description will begin with the subsequent processes.

Referring to FIG. I OA, a first conductive layer 310 for storage node electrodes Is l'on1lcd on etch stoppers 175 on which mold oxide layer patterns 190 are formed.

Thereafter, an insulating layer 320 is deposited on the first conductive layer 310 3() The lost conductive layer 310 and the insulath1g layer 320 are ansotropically etched to hong first conductive spacers 311 and insulating spacers 321 as shown m FIG. I OB A second conductive layer 330 for storage node electrodes is deposited on the resultant structure. Here, the first conductive spacers 311 contact storage node ColtrCt pluses 185 Next, by amsotropcally etching the second conductive layer 330, second conductive spacers (not shown) are fonned on the sidewalls of the insulating spacers 321. Here, the second condctvc spacers contact the storage node contact plugs 185 whlc contacting the sidewalls ol'the first conductive spacers 311. As shown in FIG. l ()(', the surl'ace oI'lhe resultant structure Is chemical mechanical polished to form f r st conductive line patterns 312 t'ormed of the first conductive spacers 311 and second conductive line patterns 332 formed of the second conductive spacers. Here, the first conductive line patterns 312 are formed mto an L-shape and portions ol'the second conductive line patterns 332 contact the lower portions of the first conductive 1() hne patterns 312. Thereafter, the insulating spacers 321 and the mold oxide layer patrons 190 are removed by a conventional wet etching method. Accordingly, storage node electrodes 300 formed of the first and second conductive line patterns 312 and 332 are fonned.

Here, the storage node electrodes 300 are formed of two conductive line l 5 palicms; however, the widths and the numbers of the conductive lme patterns can be van ed.

In addition, the mold oxide layer Is formed to be parallel to the bit line structures In the present embodiments; however, the mold oxide layer can be Donned to be par-allcl to the word brie structures as shown in the second embodiments. 2()

F'oul-tll Embodiments FIG. 12A and 12B are the sectional views cut along lines C-C' ofFIGS. 1 IA and l l B. respcctvely.

The descriptions ot'the elements that are the same as the first through third embodiments will not be rcpcatcd, and the same reference numerals are allotted for- the same elements of the f rst through third embodiments. In addition, in the present emho:hmcnts, the processes pcrfomied up until forming storage node contact plugs Or c the same as the processes of the first through third embodiments, thus the dcscnpton will begin with the subsequent processes.

3() Rcf'erring to FIGS 11 A and 12A, a mold oxide layer Is fomied on storage node contact plugs 185 and etch stoppers 175 to a Eredetermmed thickness. Here, the mold oxide layer t'or- detcnnuinig the height of storage node electrodes can be formed to the desired height of the storage node electrodes. ThereaI'ter, portions of the mold oxalic layer are dry etched to forth a plurahty of mold oxide layer patterns 400. 1 {ore, the mold oxide layer pattcnns 400 arc fonned in, for example, one- pitch intervals, while being formed m the shape of waves on a plan view. In other words, ridge portions X of the mold oxide layer patterns 400 located between the storage node contact plugs 185 and valley portions X2 of the mold oxide layer patterns 400 are located on dram regions, which correspond to first contact pads 140a, or on an isolation layer l l 0 corresponding to the drain regions. When connecting the ridge portions X' of the wave-shaped mold oxide layer patterns 40O, straight lines are longed In addition, m some embodiments, the straight lines are parallel to bit lines structures 165.

1 () As shown In FIGS. l l i] and 12B, a conductive layer 410 for storage node electrodes, liar example, a:loped polysilicon layer, is deposited on etch stoppers 175 on which the wave-shaped mold oxide layer patterns 400 are t'onned, and a buffer hisulatirig layer 420 is deposited on the conductive layer 410 for storage node electrodes. Thereui'ter, a chemical mccilanical polishing is performed to expose the mold oxide layer patterns 400. Accordingly, the conductive layer 410 for storage node electrodes remains n1 a rcgon defined by the mold oxide layer patterns 400 Here, the sidewalls of the renainng conductive layer 410 for storage node electrodes have the same wave shape as the mold oxide layer patterns 400.

Next, as shown h1 FIGS. 11 C and 13, grooves 430 are fonmcd by dry etching 2() portions of the mold oxide layer patterns 400, the conductive layer 410 t'or storage node electrodes, and the Insulating layer 420 in order to separate the storage node electrodes by ceil Here, the grooves 430 are formed between word line structures 120, on which drain regions (not shown) are formed, while being perpendicular to the extending direction of the mold oxide layer patterns 400, i.e., the direction of bit line structures. It is preferable that the grooves 430 pass through tile valley portions X2 of the mold oxide layer patterns 400.

Thereafter, as shown in FIGS. 1 ID and 14, an Insulating layer for supporters is deposited to suf'ficicntly fill the grooves 430. Here, the msulatng layer for supporters can be donned of the same material as the etch stoppers 175, for example, a silicon 3() mtnde layer She insulating layer Is wet or dry etched to a predetermined thickness so that the msulatmg layer is remanded n1 the grooves 430 to a height smaller than the height oi'the conductive layer 410 for storage node electrodes or the mold oxide layer patients 400 Accordingly, supporters 440 are formed.

The mold oxide layer pattcnns 400 and the insulating layer 420 are removed by a conventional wet etching method to f'onn storage node electrodes 425. Here, since the etch stoppers l 75 are bombed on the resultant structure on the semiconductor substrate 10() and the etching selectivity of the supporters 440 is different from the ctchmg sclectvtes of the mold oxide layer patterns 400 and the insulating layer 420, only the mold oxide layer patterns 400 and the insulating layer 420 are selectively removed. Thus, the storage node electrodes 425 are defined in cu1its of each cell In other words, the storage node electrodes 425 are separated m units of each cell by the supporters 440 m a direction parallel to the word lines. In addition, the supporters 1() 440 fornicd in specl'ic Intervals support the storage node electrodes 425, which are fomicd Into wave-shaped line pattcn1s. Therefore, the narrow and high storage node electrodes 425 are prevented from falihig toward the adjacent storage node electrodes 425.

/\ccordmg to the present embodiments, since the storage node electrodes 425 ] 5 are formed m the wave shape, the surl'ace area of the storage node electrodes 425 ucreascs In addition, since the storage node electrodes 425 are extended to the drain regions or the regions corresponding to the drain regions, the surface area of the storage node electrodes 425 further Increases.

Furthermore, since the supporters 440 are fonned to separate the storage node 2() electrodes 425 in units of each cell, the storage node electrodes 425 are reduced or prevented l;-om falling or bending toward the adjacent storage node electrodes 425.

I-lere, the mold oxide layer patterns can be formed by changing the intervals of the wave as shown m FIG. 15.

Rcl'en-ing to FIG. 15, mold oxide layer patterns 450 are Conned in the shape of waves in a plan view. Here, ridge portions X3 and valley portions X4 are formed to be located between storage node contact plugs 185. In this case, lines formed by connecting the ridge portions X3 and lines fonned by connecting the valley portions X are parallel with one another by a predetermined distance, which is wider than the width of the active regions.

If the wave shape of the mold oxide layer patterns 450 is changed, the same effect Is attained.

In addition, as shown m FIG. 16, mold oxide layer patterns 500 may be formed n1 two-ptch intervals. In other words, the mold oxide layer patterns 500 are arranged in two-pitch intervals as shown m the first embodiment while bomb t'ormeci in the shape of waves on a plan view. For example, in the mold oxide layer patterns 500, ridge portions X' may be located between storage node contact plugs 185,and valley portions X2 may be located on drain regions, net, first contact regions, or on an Isolation layer I 10 corresponding to the dran1 regions. If the mold oxide layer patterns 500 in two-pitch intervals are formed, the same effect is attained.

he addition, storage node electrodes 425 can be formed by the method performed in the third embodimcuts.

Fll'th Embodiments I 0 FIGS. 17A and 17B are plan views of stages m the manufacture of a semiconductor memory device according to fifth embodiments of the present invention. 'I'he processes perfonned Lip lentil forming etch stoppers 175 are the same as the processes oi'the first and second embodiments, thus the description will begu wits the srbscclent processes.

1<ct'erring to FICiS 17A, mold oxide layer patterns 600 are formed in the shape of waves m a plan view, on etch stoppers 175. Here, the mold oxide layer patterns 600 can be romped he, for example, one-ptch intervals. In other words, lines l'onned by connecting ridge portions X5 or valley portions X6 of the mold oxide layer patterns 600 are substantially parallel to word line structures 120. In addition, the mold oxide 2() layer patients 600 are t'ormcd to expose each ol'the storage node contact plugs 185 between the adjacent mold oxide layer patterns 600 on the same lines. The mold oxide layer patterns 600 are formed on regions without storage node contact plugs, e., on dram regions and on an isolation layer 110 corresponding to the drain r egions.

A plurahty ol'condcctvc line patterns 610 and insulating line patterns 620 are alternately t'onned between the mold oxide layer patterns 600. F1ere, the plurality of conductive hne patterns 610 and msulathl line patterns 620 are formed into waves according to the wave-shaped mold oxide layer patterns 600. In this case, the condcctvc Inane patterns 610 and the mslating line patterns 620 are fonmed by the above-descubed methods.

3() As shown In FI(:. 17B, portions ol'the mold oxide layer patterns 600, the conductive One patterns 610, and the insulating hne patterns 620 are etched to form grooves 630 The grooves 630 are formed on regions, which overlap bit hne structures 165, in order to separate the conductive line patterns 610 in units ol'each ceil. Here, the conductive Ime patterns 610 are defiecd In units of each cell by the grooves 630 and the mold oxide layer pattern 600, and the conductive Imc patterns 610 are fomled into waves while contacting the storage node contact plugs 185.

Thereat'ter, supporters (not shown) arc formed in the grooves 630 by the above-descrbcd metllod. The mold oxide layer patterns 600 and the insulating line patterns 620 are etched lo form storage node electrodes 625.

Ii'lhe mold oxide layer patterns 600 are formed to be parallel to the word hne structures 120, the same effect may be attained.

As shown in FIG. 18, the same effect may be attained by forming the mold oxide layer patterns 700 into waves in two-ptch intervals.

As described above, according to embodiments of the present invention, storage node electrocies are fomlcd m a plurality ol'hne pattern types having a fine hne wdlh. Thus, the surface area ol'the storage node electrodes can increase. In addition, the supporters formed of an ms'latulg layer are formed to be perpendicular to the extending direction of the line patterns of the storage node electrodes.

Therel'orc, the supporters separate the storage node electrodes in units of each cell, and the supporters support the storage node electrodes, thereby reducing or preventing the storage node electrodes from lolling or bending toward the adjacent storage node e lectrodes Furthermore, the regions for forming the storage node electrodes may be 2() increased so that the surface area of the storage node electrodes may be increased.

While this mventon has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes ul t'onn and details may be made therein without departing from the spirit and scope ot'thc invention as defined by the appended claims.

In the drawings anti spccficaton, there have been disclosed typical preferred embodiments of the invention and, although specific terms arc employed, they are used n1 a gcnerc and descriptive sense only and not for purposes of limitation, the scope of the invention bemg set forth in the following claims.

Claims

CLAIMS: I A method of manufacturing a semiconductor memory device, the

method comprising: deposlmg an n1terlevel insulating layer on a semiconductor substrate; t'ormmg a plurality of storage node contact plugs in the interlevel insulating layer m specific intervals; Conning mold oxide layer patters on the mtcrlevel insulating layer in specific hlervals lo expose Il1e storage node contact plugs; I'ilhug tl1c spaces between the mold oxide layer patterns by alternately formh1g I () conductive hne patterns and Insulating hne patterns, repeatedly, on sidewalls of the mold oxide layer patterns; bonding grooves perpendicular to the mold oxide layer patterns by etching portions of the mold oxide layer patterns, the conductive line patterns, and the usulain1g One patterns; and f'om1ing storage node electrodes by selectively removing the mold oxide layer patters and the nsulatmg Idle patterns.
2. The method for manufacturing a semiconductor memory device of claim 1, wherein the mold oxide layer patterns are formed so that each of the storage 2() node plugs are between adjacent mold oxide layer patterns.
3. The method for manufacturing a semiconductor memory device of clanks I or 2, wherein the mold oxide layer patterns are foamed so that two storage node plugs arc between the adjacent mold oxide layer patterns on the same lines.
4. 'the method for manufacturing a semiconductor memory device of claim I, 2 or 3, wherein the mold oxide layer patterns are formed into straight lines in a plan vice 3()
5. The method for manufacturing a semiconductor memory device of claim I, 2 or 3, wherein the mold oxide layer patterns are formed in the shape of waves on a plan view h1 order to form the conductive brie patterns into waves no the plan view.
6 The method for manufacturing a semiconductor memory device of any of clams I to 5, wheren1 the fillmg of the spaces between the mold oxide layer patterns Smug the conductive hne patterns and the insulating line patterns comprises: forrniny, conductive spacers on the sidewalls of the mold oxide layer patterns; I'onnm, Insulating spacers on the sidewalls of the conductive spacers; repeathlg the Conning of the conductive spacers and the fonnmg of the msulatng spacers at least once; and chemical mecllamcal polishing the mold oxide layer, the conductive spacers, and the msulatr1g spacers to form the conductive line patterns and the insulating line I () patterns.
7. The method for manut'acturmgasemrconductor memory device of clan 6, wherein the conductive spacers are formed to contact the storage node contact plugs.
S. The method for manufacturing a semiconductor memory device of clang 6 or 7, wherein the insulating spacers are finally Longed when repeatedly f'onnng the conductrvc spacers and the insulating spacers.

2()
9. The method t'or manut'acturirlg a semiconductor memory device of any ot'claulls I to 5, wherein the filling of the spaces between the mold oxide layer patten1s using the conductive line patterns and the insulating line patterns composes.

depostmg a first conciuctive layer on the mterlevel insulating layer and the mold oxide layer patterns; fomnng an insulating layer on the first conductive layer; forming first conductive spacers and insulating spacers by ansotropcally ctchng the n1sulatng layer and the first conductive layer; formmg second conductive spacers on the sidewalls ofthe insulating spacers; Multi 3() chemical mecl1arlcal poUshmg the mold oxide layer patterns, the first conductive spacers, the insulating spacers, and the second conductive spacers.
10. The method for manufacturing a semiconductor memory device of any of claims I to 9, I;rtller compnsulg fomlmg supporters m the grooves between the l'onning of the grooves and the t'ormhg of the storage node electrodes.
11. The method for manufacturing a semiconductor memory device of clam I (), wherein the l'omnl, supporters eomprses: depostmg an insulating layer to fill the grooves; and etching the hsulathlg layer so the insulathlg layer remams in the grooves.

I ()
12. The method l'or manul'acturmg a semiconductor memory device of clam 11, wherein the insulating layer is etched by a wet etching method.
13. The method for manufaeturulg a semiconductor memory device of clams I I or 12, wherein the insulating layer is etched to have a height smaller than the height of the conductive line patterns.
14. The method for manufacturing a semiconductor memory device of claull I 1, 12 or 13, wherein, the insulating layer comprising the supporters has an etchhlg selectivity dil'ferent from the etehhlg seleetivites of the mold oxide layer patterns and the nsulatmg line patterns.