GB2022299A - Multi-processor systems using microprocessors - Google Patents

Multi-processor systems using microprocessors

Info

Publication number
GB2022299A
GB2022299A GB7919513A GB7919513A GB2022299A GB 2022299 A GB2022299 A GB 2022299A GB 7919513 A GB7919513 A GB 7919513A GB 7919513 A GB7919513 A GB 7919513A GB 2022299 A GB2022299 A GB 2022299A
Authority
GB
United Kingdom
Prior art keywords
processor
bus
slave
acknowledgement
master processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7919513A
Other versions
GB2022299B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB2022299A publication Critical patent/GB2022299A/en
Application granted granted Critical
Publication of GB2022299B publication Critical patent/GB2022299B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

In a multi-processor system a plurality of microprocessors (1,2) are coupled to a common system bus (10). A master processor (2) has a hold input (33) (HOLD) for bus requests from other processor(s), and an output (34) (HOLDA) for the emission of an acknowledgement confirming that no further access to the system bus by the master processor will take place for the duration thereof. A second slave processor (1) has a transmitter (BUS REQ) for the emission of bus requests requesting access to the system bus to the hold request input of the master processor, and a receiver (BRPI) for receiving the acknowledgements from the acknowledgement output of the master processor which inform the slave processor of its entitlement to access to the system bus. The slave accesses the bus only during receipt of the acknowledgement. Where more than one slave processor is provided the acknowledgement signal from the master processor is fed to a first one of the slaves and is forwarded to successive slaves until it reaches the slave which made the bus request. Alternatively to save time logic may be provided to route the acknowledgement directly to the requesting slave. <IMAGE>
GB7919513A 1978-06-05 1979-06-05 Multi-processor systems using microprocessors Expired GB2022299B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19782824557 DE2824557C2 (en) 1978-06-05 1978-06-05 Arrangement in microprocessors for the construction of multiprocessor systems

Publications (2)

Publication Number Publication Date
GB2022299A true GB2022299A (en) 1979-12-12
GB2022299B GB2022299B (en) 1982-06-23

Family

ID=6041047

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7919513A Expired GB2022299B (en) 1978-06-05 1979-06-05 Multi-processor systems using microprocessors

Country Status (5)

Country Link
JP (1) JPS54159842A (en)
BR (1) BR7903495A (en)
DE (1) DE2824557C2 (en)
FR (1) FR2428283A1 (en)
GB (1) GB2022299B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0050305A1 (en) * 1980-10-20 1982-04-28 Inventio Ag Unit to control the access of processors to a data bus
EP0155443A1 (en) * 1984-03-19 1985-09-25 International Business Machines Corporation Microocomputer data processing systems permitting bus control by peripheral processing devices

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4412281A (en) * 1980-07-11 1983-10-25 Raytheon Company Distributed signal processing system
JPS60258671A (en) * 1984-06-05 1985-12-20 Nec Corp Processor
DE10149296B4 (en) * 2001-10-05 2007-01-04 Siemens Ag Multiprocessor system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0050305A1 (en) * 1980-10-20 1982-04-28 Inventio Ag Unit to control the access of processors to a data bus
EP0155443A1 (en) * 1984-03-19 1985-09-25 International Business Machines Corporation Microocomputer data processing systems permitting bus control by peripheral processing devices

Also Published As

Publication number Publication date
DE2824557C2 (en) 1983-01-20
DE2824557A1 (en) 1979-12-06
GB2022299B (en) 1982-06-23
BR7903495A (en) 1980-01-22
JPS54159842A (en) 1979-12-18
FR2428283A1 (en) 1980-01-04

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee