JPS61210463A - Data transfer control system - Google Patents

Abstract

PURPOSE:To shorten transfer preparing time and bus occupying time by providing a bus control circuit having a response section instantaneously responding a pseudo-bus permission signal and a ready signal with respect to a bus request signal of a transfer control circuit. CONSTITUTION:When a bus line request device 1 feeds a transfer request signal A to a transfer control circuit 2, the circuit 2 feeds a bus request signal B to a bus control circuit 8. The circuit 8 receives the signal B in a response section 8-1. The response section 8-1 feeds the signal B to a bus managing section 4 through a system bus 3 and responds a pseudo-bus permission signal and a ready signal E to the circuit 2. The circuit 2 receives the pseudo-bus permission signal and transmits it to a processing section. The processing section starts a transfer preparation by the pseudo-bus signal and extends a bus transfer cycle by the inputted signal E. The managing section 4 determines an allocation of the bus, feeds a bus permission signal C to the circuit 8. The circuit 8 outputs a bus permission acknowledgement signal D to release the signal E. Thereby, a transfer preparation time is shortened and a bus occupying time can be shortened.

Description

[Detailed Description of the Invention] [Summary] A bus control circuit is attached to a system consisting of a bus line request device and a transfer control circuit, and the bus control circuit immediately grants pseudo bus permission based on the bus request signal of the transfer control circuit. The bus occupancy time is shortened by sending out a signal and a ready signal to hasten the start of preparation for operation of the transfer control circuit, and by using the ready signal to extend the transfer cycle until the reception of a bus permission signal.

[Industrial application field]

The present invention relates to a data transfer control method for reducing bus line occupation time in a system comprising a bus line request device and a transfer control circuit that performs transfer control in response to a transfer request from the bus line request device.

The bus line connects the central processing unit and various terminal devices or
It is shared by input/output devices, that is, bus line request devices.

Therefore, each bus line requesting device sends a transfer request signal to the transfer control circuit, and the transfer control circuit determines the bus line assignment based on the instructions from the bus management section using the transfer request code and controls the transfer. ing.

Therefore, it is necessary to reduce the bus occupation time of each bus line requesting device.

[Conventional technology]

FIG. 3 is a block diagram of a conventional data transfer control system, in which a bus line request device 1 sends a transfer request signal A to a transfer control circuit 2. In FIG. Transfer control circuit 2 receives transfer request signal A and sends bus request signal B to bus management section 4 via system bus 3.

The bus management unit 4 that manages the system bus 3 sends a bus permission signal C if it is possible to permit use of the system bus 3.
is responded to the transfer control circuit 2.

! The transfer control circuit 2 starts preparation for transfer in response to the bus permission signal C, and after completing the preparation, sends out a bus permission positive signal to cause the transceiver 5 to use the data bus 6.

The transceiver 5 operates using the local data bus 7 under its jurisdiction.

The conventional time chart mentioned above is as shown in FIG.

That is, the transfer control circuit 2 starts preparing for transfer after receiving the bus permission signal C.

[Problem that the invention seeks to solve]

As described above, the transfer preparation of the conventional transfer control circuit has to wait until the bus permission signal is received, and as a result, there is a problem in that the bus line requesting device occupies the bus for a longer time.

[Means for solving the cria point] A bus control circuit is attached to the transfer control circuit, and the bus control circuit immediately responds with a pseudo bus permission signal and a ready signal to the bus request signal of the transfer control circuit. It is configured to provide a section.

[Effect]

The transfer control circuit sends a bus request signal, prepares for transfer in response to a pseudo bus permission signal from the response unit, and waits for the transfer cycle to be completed by the response unit's ready signal until the bus permission signal is responded to, thereby completing the preparation time. Bus occupancy time can be reduced.

〔Example〕

FIG. 1 shows an embodiment of the present invention, which differs from the conventional example in that a bus control circuit 8 is attached to the transfer control circuit 2, and this bus control circuit 8 includes a response section 8-1. .

When the bus line requesting device 1 sends a transfer request signal A to the transfer control circuit 2, the transfer control circuit 2 sends a bus request signal B to the bus control device 8. In the bus control device 8, the response unit 8-1 receives the bus request signal B, and the response unit 8-1 sends the bus request signal B to the bus management unit 4 via the system bus 3, and also sends the bus request signal B to the bus management unit 4 via the system bus 3. A signal CI and a ready signal E are sent to the transfer control circuit 2 in response.

The transfer control circuit 2 receives the DI (12 bus permission signal C1) and notifies the processing unit 2-2 of this fact.

The processing unit 2-2 starts preparation for transfer in response to the pseudo bus signal CI, and extends the bus transfer cycle in response to the input ready signal E.

On the other hand, the bus management unit 4 that has received the bus request compensation signal B determines bus assignment and sends a bus permission signal C to the bus control circuit 8.

When the bus control circuit 8 receives the bus permission signal C, it outputs a bus permission affirmation signal and releases the ready signal E.

A second time chart of the present invention is shown. As shown in the figure, the transfer control circuit 2 outputs the bus request signal B, and upon receiving the pseudo bus permission signal C1, prepares for transfer. Therefore, the bus occupation time for transfer preparation is shortened.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to reduce the transfer preparation time, which is extremely useful in reducing the bus occupation time.

[Brief Description of the Drawings] Figure 1 is a block diagram of an embodiment of the present invention, Figure 2 is a time chart of the present invention, Figure 3 is a block diagram of a conventional data transfer method, and Figure 4 is a block diagram of a conventional data transfer method. This is a time chart. In the figure, 1 is a bus line requesting device, 2 is a transfer control circuit, 3 is a system bus, 5 is a transceiver, 8 is a bus control circuit, and 8-1 is a response section. 1st birth of sulfur day H

Claims (1)

[Scope of Claims] A system comprising a bus line request device (1) and a transfer control circuit (2) that performs transfer control based on a transfer request from the device (1), wherein the transfer control circuit (2) includes a bus control circuit. (8), and a response unit (8-) for immediately responding to the bus request signal of the transfer control circuit (2) with a pseudo bus permission signal and a ready signal to the transfer control circuit (8). 1), the transfer control circuit (2) prepares for transfer based on the pseudo bus permission signal of the response unit (8-1), and uses the ready signal to postpone the transfer cycle until the bus permission signal arrives. A data transfer control method characterized by line acquisition.