JPH0447433A - Multi-processor control system - Google Patents

Abstract

PURPOSE:To eliminate the deterioration of the whole data processing capacity of a personal computer system without necessitating such a complicated hardware as a bus arbitration circuit by adjusting a collision of a bus obtaining request from each processor. CONSTITUTION:A bus obtaining instruction control means 5a of a processor 1a sends out a bus obtaining instruction signal to a bus obtaining request signal sending-out means 8a. The means 8a which receives the instruction signal sends out a request signal to a processor 1b by using a control bus 4. On the other hand, an execution control means 6a receives the instruction signal and controls an obtaining means 7a to a bus obtaining execution sate. In such a way, the processor comes to be able to transfer data to a common storage device 2 through a data bus 3. The whole data processing capacity of a personal computer system can be prevented from being deteriorated.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a multiprocessor control system, and in particular, in a personal computer system configured with a plurality of processors, each processor has a storage device commonly used by each processor. This paper relates to a multiprocessor control method when transferring data between machines.

[Conventional technology]

Conventionally, in a personal computer system consisting of a plurality of processors, when data is transferred between the processors 9 a y 9 b and the common storage device 2, as shown in FIG. If bus acquisition requests occur at the same time, there will be a conflict between the bus acquisition requests from two processors, and control is such that if one processor acquires the bus, the other processor will not be able to acquire the bus. . Therefore, a bus arbitration mechanism 10, which is an adjustment circuit for adjusting bus acquisition requests from the processors 9a and 9b, is required. A bus arbitration mechanism 10 performs conflict adjustment control for the processing of a processor that cannot acquire a bus due to a collision of acquisition requests.

[Problem to be solved by the invention]

The conventional multiprocessor control method described above requires a bus arbitration mechanism to coordinate bus acquisition requests from multiple processors. There is a problem in that the data processing capacity of the personal computer system as a whole is reduced because of the need for control.

It is an object of the present invention to reduce the overall data processing capacity of a personal computer system without requiring complex hardware such as a bus arbitration circuit for coordinating conflicts between bus acquisition requests from each processor. An object of the present invention is to provide a multiprocessor control method that can eliminate the deterioration of performance.

[Means to solve the problem]

In the multiprocessor control system of the present invention, a plurality of processors connected to a common data bus and transmitting and receiving data to and from the data bus by a bus acquisition means are connected to the data bus and commonly used by the plurality of processors. In a multiprocessor control method for transferring data to and from a storage device, the processor: (A) based on a bus acquisition request signal from another processor;
bus acquisition instruction control means for outputting an instruction signal instructing whether to acquire a bus; (B) bus acquisition execution control means for receiving an instruction signal instructing whether to acquire a bus and controlling the bus acquisition means; ) bus acquisition request signal sending means for receiving an instruction signal instructing whether or not to acquire the bus, and controlling sending of the bus acquisition request signal to other processors;

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

When the multiprocessor control method shown in FIG. 1 receives a bus acquisition request signal from another processor, it outputs a bus acquisition standby instruction signal and stops sending the bus acquisition request signal from the other processor. in a state where
Bus acquisition instruction control means 5 a t5b1 which outputs a bus acquisition instruction signal when a data transfer request with the common storage device 2 occurs; processor bus acquisition means 7 a r which receives a bus acquisition waiting child signal; The bus acquisition execution control means 6a and 6b1 which control the bus acquisition means 7a*7b to the bus acquisition standby state, receive the bus acquisition instruction signal, and control the bus acquisition means 7a*7b to the bus acquisition execution state. The bus acquisition request signal transmitting means 8a and 8b transmit a bus acquisition request signal to other processors when the bus is used, and stop transmitting the bus acquisition request signal when the bus is no longer used.

Next, the operation will be explained.

In FIG. 1, for example, when processor 1a transfers data to/from common storage device 2, bus acquisition instruction control means 5a of processor 1a sends a bus acquisition instruction signal to bus acquisition request signal sending means 8a. The bus acquisition request signal sending means 8a that has received the bus acquisition instruction signal sends the bus acquisition request signal to the processor 1b using the control bus 4.

On the other hand, the bus acquisition execution control means 6a receives the bus acquisition instruction signal and controls the bus acquisition means 7a to a bus acquisition execution state. This allows the processor to transfer data to and from the common storage device 2 via the data bus 3.

While processor 1a has acquired bus 3 and is using it,
To get bus 3 and let it know it's in use,
A bus acquisition request signal is continuously sent out from the bus acquisition request signal sending means 8a.

The processor 1b monitors the reception of the bus acquisition request signal of the processor 1a via the control bus 4 by the bus acquisition instruction control means 5a until the data transfer of the processor 1a is completed. When the processor 1b needs to transfer data, when the reception of the bus acquisition request signal stops due to the completion of the bus data transfer by the processor 1a, the bus acquisition instruction control control means 5b controls the bus acquisition execution control by using the bus acquisition instruction signal. It is sent to means 6b. Upon receiving the bus acquisition instruction signal, the bus acquisition execution control means 6b performs bus acquisition control and acquires the data bus 3. Furthermore, the bus acquisition request signal sending means 8b that has received the bus acquisition instruction signal sends a bus acquisition request signal to the processor 1a using the control bus 4.

In this way, by having both processors la and lb alternately perform bus acquisition data transfer, a bus arbitration mechanism is not required, and the data processing capacity of the personal computer system as a whole can be reduced. .

Note that in the above description, processor 1a and processor 1
The control bus 4 was used to send the bus acquisition request signal between the processors 1a and 1b, but a communication line was provided directly between the processors 1a and 1b, and the bus acquisition request signal was sent via this communication line. Sending may also be performed.

〔Effect of the invention〕

As explained above, the present invention eliminates the need for complex hardware such as a bus arbitration circuit, and allows each processor to request bus acquisition alternately when transferring data to and from a storage device. This has the effect of preventing a decline in the data processing capacity of the computer system as a whole.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional multiprocessor control system. la, lb...processor, 2...common storage device, 3...data bus, 4...
・Special a bus, 5a. 5b...Bus acquisition instruction control means, 6a, 6b.
...Bus acquisition execution control means, 7a, 7b...
...Bus acquisition means, 8a+8b...Bus acquisition request signal sending means, 9a, 9b...Processor, 10...Bus arbitration mechanism. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Scope of Claims] 1. A plurality of processors connected to a common data bus and transmitting/receiving data to/from the data bus by a bus acquisition means, a plurality of processors connected to the data bus and commonly used by the plurality of processors. In a multiprocessor control method for transferring data to and from a storage device, the processor: (A) based on a bus acquisition request signal from another processor;
bus acquisition instruction control means for outputting an instruction signal instructing whether to acquire a bus; (B) bus acquisition execution control means for receiving an instruction signal instructing whether to acquire a bus and controlling the bus acquisition means; ) bus acquisition request signal sending means for receiving an instruction signal instructing whether or not to acquire the bus, and controlling sending of the bus acquisition request signal to other processors; . 2. between a plurality of processors connected to a common data bus and transmitting and receiving data to and from the data bus by means of bus acquisition means, and a storage device connected to the data bus and used commonly by the plurality of processors; In a multiprocessor control system for performing data transfer in a multiprocessor control system, the processor (A) outputs a bus acquisition standby instruction signal when it receives a bus acquisition request signal from another processor, and receives a bus acquisition request signal from the other processor. (B) bus acquisition instruction control means for outputting a bus acquisition instruction signal when a data transfer request with the storage device occurs while transmission of the bus acquisition request signal is stopped; (C) bus acquisition execution control means for receiving a standby instruction signal to control the bus acquisition means to a bus acquisition standby state, and receiving a bus acquisition instruction signal to control the bus acquisition means to a bus acquisition execution state; When the bus acquisition instruction control means receives the bus acquisition instruction signal from another processor without receiving the bus acquisition request signal of the other processor, it sends the bus acquisition request signal to the other processor, A multiprocessor control system comprising: bus acquisition request signal sending means for stopping sending of the bus acquisition request signal when use is completed.