JPS6272053A - Processor unit - Google Patents

Abstract

PURPOSE:To shorten widely the waiting time by receiving the task request for the number of the set receiving buffer only and receiving the enquiry response. CONSTITUTION:When the task request to a processor unit 100 occurs at a processor unit 102, the accumulating of the task request for the processor unit 100, which is the transmitting information, to a transmitting buffer memory 40 through a processor interface part 20 is executed, the setting of the empty selection to a transmitting control part 60 is executed, the designation of the data transferring bus between processors used for the transmission is executed and thereafter, the transmitting execution is instructed. At a bus 0 interface part 70, the transmitting permission is sent, the information is received, and thereafter, a processor 10 sets the equipment busy condition as the receiving condition to a bus 0 receiving control part through the processor interface part 20. Thus, respective receiving buffers can receive one task request or the enquiry, and after all, the task request or the enquiry for the number of the set receiving buffer only can be received.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a processor unit used in a multiprocessor system in which each processor unit communicates via two or more sets of inter-processor data transfer buses.

(Prior art) A load-distributing multiprocessor system in which multiple stages of individual single-task processor units are connected to each other via a data transfer bus, with the aim of improving system processing power and simplifying the software configuration of the processor units. However, if there is inquiry processing for other processor units during a task executed in each processor unit, the reception buffer of the inter-processor data transfer bus is constantly monitored during task execution, and the reception It is necessary to determine whether the received message is another new task request or a response to an inquiry.

This is because the above processor unit can only execute a single task, so if the received message is a response to an inquiry, there is no problem, but if it is a request for another new task, the requester will be notified that the request cannot be executed. This is because the processor unit must be notified.

However, as can be easily imagined, if the above judgment and response were executed by software, the software processing time in each processor unit would increase, making it difficult to increase the processing capacity.

In order to compensate for this drawback, the following inter-processor data transfer method has been proposed. This has two mutually exclusive reception states, a device busy state and a device idle state, in each processor unit, and means for setting either of them in each processor unit, and furthermore, the reception state of the destination processor unit. Means having an empty selection transmission request to which transmission permission is granted when the device is in an idle state and a busy selection transmission request to which transmission permission is granted when the device is in a busy state, and specifying which one to use. This is a method of providing hardware.

That is, when each processor unit needs to request a task to another processor unit, it transmits an empty selection transmission request to the other processor unit, and after receiving transmission permission, transmits the task request.

On the other hand, a processor unit that has accepted a task request from another processor unit sets its receiving state to a device busy state, and other processor units that respond to inquiries from the processor unit set to a device busy state are not set to a device busy state. Send response information with a medium selection transmission request. Therefore, the new task request is an empty selection transmission request, and on the other hand, since the processor unit that is executing the task is in a device busy state, transmission permission is not granted, and the software judges the information received and sent and sends a new request. There is no need to notify users that certain tasks cannot be executed.

(Problems to be Solved by the Invention) However, since the above-mentioned conventional technologies are all single-task systems, if an inquiry is made to another processor unit during the execution of a task, the processor unit executing the task will receive an inquiry. Waiting time for a response occurs as completely wasted time that has nothing to do with the processing time required to actually execute the task, and if there are many inquiries to other processor units during task execution, the inquiry time will take up less of the task execution time. The disadvantage is that the ratio becomes large and the advantages of multiprocessorization cannot be fully utilized.

In order to reduce the waiting time for responses to inquiries, it is necessary to adopt a multitasking system, but in a multiprocessor system using conventional hardware-configured processor units, trying to adopt a multitasking system requires software that is extremely complex. There was a problem that the scale of the project would increase the burden.

The purpose of the present invention is to solve the problems of the prior art described above.
The software configuration in each processor unit is
The present invention aims to provide a processor unit that can realize a multitasking system with a configuration as simple as that of a singletasking system.

(Means for Solving the Problems) The present invention has the following configuration to achieve the above object. That is, the multitask processor unit of the present invention has the following features:
a processor; a plurality of bus interface units provided corresponding to each system of the plurality of connected inter-processor data transfer buses; a reception unit that stores information received via each of the transfer buses for each transfer bus; Buffer memory unit: Provided for each transfer bus, and according to a command from the processor, when information for executing a task is not received via the transfer bus, a device empty state is set, and after receiving the information, A device busy state is set, and according to the set device state, the corresponding bus interface section grants transmission permission to all selection transmission requests that arrive when the device is idle, and sends permission to send requests that arrive when the device is busy. a reception control unit that controls the bus interface unit so as to grant transmission permission to the selected all-selection transmission request and to grant transmission permission to the busy selection transmission request, and also controls the reception buffer memory unit; a transmission buffer memory section for accumulating information to be transmitted; and a transmission buffer memory section that controls selection of an empty or busy transmission request, selection of a transmission transfer bus for a bus interface section, and control of the transmission buffer memory section according to instructions from the processor. and a transmission control unit that performs the transmission.

(Function) The processor unit of the present invention has a plurality of circuits (referred to as receive buffers) each consisting of a bus interface section, a reception control section, and a reception buffer memory, and each bus interface section commonly connects the processor unit. The processors are connected to different transfer buses among a plurality of inter-processor data transfer buses. The receive buffer is in the device empty state while it is not receiving information for task execution from other processor units, and after receiving it, it is in the device busy state. 0 When the device is in the empty state, it does not accept task requests or inquiries from other processor units When an all-select transmission request (a preliminary signal indicating a desire to transmit) arrives, the bus interface section grants transmission permission and receives the transmission of information for task execution.

On the other hand, when the device is in a busy state, the bus interface section does not grant transmission permission even if an all selection transmission request comes, but grants transmission permission when a busy selection transmission request comes. On the other hand, for transmission, the transmission control unit selects an all selection transmission request when making a task request or inquiry to another processor unit, and a busy selection transmission request when sending a response to an inquiry. Furthermore, the transmission control section controls the bus interface section in order to select a transfer bus for transmission.

Therefore, in the processor unit of the present invention, each receive buffer can accept one task request or inquiry, and in the end, the processor unit can accept as many task requests or inquiries as the number of reception buffers provided. be able to.

Also, even if the receive buffer accepts task requests,
Responses to inquiries made to other processor units in executing the task can be accepted even when the device is busy.

Therefore, if the processor is currently executing a task accepted in the 0th receive buffer and it becomes necessary to request a task or make an inquiry to another processor unit, the result or response will be The execution of the task in the processor is suspended until it returns, but during that time, for example, it is possible to execute the accepted task in the first receive buffer, and as long as there is an accepted task, the accepted task will be executed. It is possible to prevent the processor from being idle.

This means that the waiting time when a processor unit issues a task execution request or makes an inquiry to another processor unit while executing its own task is greatly reduced. It means to do something.

The software configuration in each processor unit for realizing this is comparable to the software configuration of a single-task system.

That is, in a multiprocessor system using the processor unit of the present invention, a multitask system can be realized with a software configuration in each processor unit as simple as a single task system.

(Example) Next, an example of the processor unit of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a processor unit according to the present invention. This embodiment shows two sets of processors, a 0th processor data transfer bus 110 and a 1st interprocessor data transfer bus 111. 1 shows a processor unit 100 to which an inter-data transfer bus is connected.

The 0th inter-processor data transfer bus 110 is connected to a bus 0 reception buffer 80 and a transmission buffer 90 via a bus 0 interface section 70, respectively. Similarly, the first inter-processor data transfer bus 111 is connected to a bus 1 reception buffer 81 and a transmission buffer 90 via a bus 1 interface section 71, respectively. On the other hand, processor 10
is connected to bus 0 via the processor interface section 20.
Receive buffer 80. It is connected to bus 1 receive buffer 81 and transmit buffer 90.

The bus O reception buffer 80 includes a bus O reception buffer memory section 30 that stores information received via the O-th inter-processor data transfer bus 110, and a bus O reception buffer memory section 30 that stores information received via the O-th inter-processor data transfer bus 110. Bus O for setting one of two types of reception status
The bus O reception control section 50 controls the bus 0 interface section 70 and the bus 0 reception buffer memory section 30 according to the set reception state. Similarly, the bus 1 reception buffer 81 stores the information received via the first inter-processor data transfer bus 111 and the bus 1 reception buffer memory unit 31 and the processor interface unit 20. It consists of a bus 1 reception control section 51 that sets one of two reception states (busy state), and the bus 1 reception control section 51 controls the bus 1 interface section 71 and the bus 1 reception buffer memory according to the set reception state. Part 31
control each.

The transmission buffer 90 is connected to a 0th inter-processor data transfer bus 110 or a 1st inter-processor data transfer bus 111.
The transmission buffer memory unit 40 stores information to be sent to other processor units via the processor interface unit 20, and the processor 10 determines which of the two types of transmission requests, empty selection and busy selection, to use. and a transmission control unit 60 that sets which of the two sets of inter-processor data transfer buses will be used for transmission. Controls the interface section and the transmission buffer memory section 40.

FIG. 2 shows a processor unit 100 according to the present invention shown in FIG. 1 and a processor unit 10 having the same configuration.
1 is a block diagram showing an embodiment of an inter-processor data transfer system configured by processor units 1 to 103, each of which has a 0th inter-processor data transfer bus 110 and a 1st inter-processor data transfer bus 1.
11.

In this embodiment, when each processor unit is not executing a task, the processor 10 in each processor unit communicates with the bus 0 reception control unit 50 and the bus 1 reception control unit, respectively, via the processor interface unit 20. 51 as the receiving state, and set the device busy state when executing a task or waiting for response information to an inquiry to another processor unit. Also, when transmitting, set the equipment idle state as the receiving state. When transmitting task request information, the processor 10 sends the transmission control unit 60 via the processor interface unit 20.
If the response information to an inquiry from another processor unit is to be sent, the busy selection is set.

Next, the communication operation of the processor unit will be explained. When a task request for the processor unit 100 occurs in the processor unit 102, the following operations are performed inside the processor unit 102. That is, the Bromo Sosa 10 stores task requests for the processor unit 100 corresponding to transmission information in the transmission buffer memory 40 via the processor interface section 20, sets empty selection to the transmission control section 60, and stores interprocessor data used for transmission. Each transfer bus is designated, and then transmission execution is commanded.

Now, if we specify the 0th inter-processor data transfer bus 110 as the inter-processor data transfer bus used for transmission, the transmission control unit 60 controls the bus interface unit 7.
0, the O-th inter-processor data transfer bus 110
Sends a request to send an empty selection. In response to this empty selection transmission request, in the processor unit 100, the bus 0 corresponding to the data transfer bus 110 between the Oth process...
Since the device empty reception state is set in the reception monitoring unit 50, the bus O interface unit 70 determines that the received transmission request corresponds to its own reception state, and immediately switches the first processor data transfer bus 111, and after receiving the information, the processor 10 sets the device busy state as the receiving state in the bus 0 reception control section 50 via the processor interface section 20.

Therefore, in the processor unit 100, in response to an empty selection transmission request sent via the 0th inter-processor data transfer bus 110, the bus 0 interface unit 70 determines that the self-receiving state and the transmission request do not correspond. It is determined that the -cut transmission permission is not granted, that is, the processor unit 100 will not accept another new task request via the 0th inter-processor data transfer bus 110.

On the other hand, since the device idle reception state is still set in the bus 1 reception control section 51 in the processor unit 100, transmission is permitted in response to an idle selection transmission request sent via the first processor leap data transfer bus 111. can be given.

That is, it is possible to accept and accept only one task request with the same operation as on the 0th inter-processor data transfer bus side.

On the other hand, while each processor unit is executing a task based on the above-described task request, there may be a need for communication such as inquiries to other processor units. Now, when the processor unit 100 is executing a task in response to a task request received via the 0th inter-processor data transfer bus 110, if it becomes necessary to make an inquiry to the processor unit 101, the above task request The processor unit 101 that receives the 0 inquiry information sends the inquiry information to the processor unit 101 via the first processor data transfer bus 111 in the same manner as in the case of sending the 0 inquiry information to the transmission control section 70 to select busy. The response information is transmitted via the 0th inter-processor data transfer bus 110.

That is, the bus O reception control unit 50 of the processor unit 100 does not grant permission to the empty selection transmission request because the device busy reception state is set because the task is being executed. In response to the incoming busy selection transmission request, the bus O interface unit 70 determines that it corresponds to the own receiving state and grants transmission permission, so that response information to the inquiry can be received.

As described above, each processor unit can accept only one task corresponding to the inter-processor data transfer bus, and can also establish communication with a specific processor unit during task execution.

(Effects of the Invention) Since the processor unit of the present invention has the configuration and operation described above, one task request per receiving buffer and inquiries made to other processor units via the receiving buffer can be made. Therefore, it is possible to receive as many task requests and inquiry responses as there are reception buffers provided.

Then, while a processor is executing a task that has been accepted by one of the receive buffers, it becomes necessary to make a task request or inquiry to another processor, and during the waiting time until a response arrives, Since the processor can execute the task one step ahead of the receiver, as long as there is a task assigned to the receiver, the processor can be operated without idleness, and the waiting time can be significantly reduced compared to a single-task system.

The software configuration in each processor unit to achieve this is comparable to the software configuration in a single-task system, so in a multiprocessor system using the processor unit of the present invention, the software configuration in each processor unit is The effect is that a multitasking system can be realized with a configuration as simple as that of a single-tasking system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a processor unit of the present invention, and FIG. 2 is a configuration diagram of a multiprocessor system using a plurality of processor units of the present invention shown in FIG. 10...Processor, 20...Processor interface section, 30...Bus O
Reception buffer memory section, 31... Bus 1 reception buffer memory section, 40... Transmission buffer memory section, 50... Bus O reception control section, 51.
... Bus 1 reception control section, 60 ... Transmission control section, 70 ... Bus 0 interface section,
71... Bus 1 interface section, 80...
... Bus O reception buffer, 81 ... Bus 1 reception buffer, 90 ... Transmission buffer, 1
00-103...Processor unit, 110
...0th inter-processor data transfer bus, 111
...First inter-processor data transfer bus. Agent Patent Attorney Yoshi Hachiman Esho Hiromoto's Inumitsu Example of T7t Tsusa Unit Figure 1 11θ ------*0 Pro 1-1 Theta Transfer Buzz/II --- -11st G17tzYrJte:-,v
Zero iys dormitory 2 diagram

Claims (1)

[Claims] A processor; a plurality of bus interface units provided corresponding to each system of a plurality of connected inter-processor data transfer buses; and a reception unit that stores information received via each transfer bus for each transfer bus. Buffer memory unit: Provided for each transfer bus, and according to a command from the processor, when information for executing a task is not received via the transfer bus, the device is set to an empty state, and after receiving the information, A device busy state is set, and according to the set device state, the corresponding bus interface section grants transmission permission to an empty selection transmission request that arrives when the device is idle, and sends a request that arrives when the device is busy. a reception control unit that controls the bus interface unit so as to grant transmission permission to an empty selection transmission request and to grant transmission permission to a busy selection transmission request, and also controls the reception buffer memory unit; a transmission buffer memory section for accumulating information to be transmitted; and a transmission buffer memory section that controls selection of an empty or busy transmission request, selection of a transmission transfer bus for a bus interface section, and control of the transmission buffer memory section according to instructions from the processor. A processor unit characterized in that it has a transmission control section that performs the following operations.