JPH0342741B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a data exchange that configures transmitted and received data into predetermined frames and performs exchange processing, and particularly relates to a main control unit constituting the data exchange and a system connected to a plurality of lines. Data transfer to configure a predetermined frame between multiple line control units that transmit and receive serial data and process each data, using the output of the bus control unit that controls the connection buses according to instructions from the main control unit. Regarding the method.

(b) Technical background FIG. 1 is a diagram showing the configuration of a packet processing device as an example of a data processing device to which the present invention is applied. In FIG. 1, a main control unit MCU is connected to a plurality of line control units LCU via a bus control unit BCU that controls a connection bus B. Each line control section
The LCU accommodates a plurality of lines L that transmit packets having a predetermined frame structure as illustrated in FIG. and error detection control using the frame check sequence FCS, and transmits the data in the information section I to the main control section MCU via the bus control section BCU, where it is stored as a data block in a predetermined format. In addition, in the case of transmission, the main control unit
A flag sequence F, an address part A, a control part C, and a frame check sequence FCS are added to the information part I in the data transmitted from the MCU via the bus control part BCU to create a packet of a predetermined frame shown in FIG. It is generated and transmitted to a predetermined line L.
The main control unit MCU analyzes and processes data transmitted from the line control unit LCU, and controls packet exchange transfer processing between lines L, etc. The bus control unit BCU is
Controls data transfer between the main control unit MCU and line control unit LCU via bus B, transmits memory access requests directly to the main control unit MCU and line control unit LCU, and controls the main control unit MCU and line control unit. The memory RAM in the main control unit MCU and line control unit LCU is temporarily suspended.
Data is directly transferred between the data buffer areas provided in the data buffer area to complete a predetermined frame configuration.

(c) Prior Art and Problems FIG. 3 is a diagram showing an example of a conventional line control section. In FIG. 3, when data transfer is requested by an instruction from the main control unit MCU, the direct memory access unit DMA transmits a direct memory access request to the direct memory access control unit DMC based on the instruction from the processor MPU. The direct memory access control unit DMC controls each direct memory access unit.
Performs conflict processing for direct memory access requests transmitted from the DMA, instructs the selected direct memory access unit DMA to start a direct memorial access, and stops the clock supply to the processor MPU via the clock control unit CLC. and temporarily suspends internal processing. The direct memory access unit DMA, which has received the instruction from the direct memory access control unit DMC, writes and reads the data constituting the packet that has arrived at the receiver/transmitter unit URT, and stores it in the memory.
The data is sequentially transferred to a predetermined data buffer area provided with RAM. Note that when the data buffer area becomes full with transfer data, the direct memory access unit DMA notifies the processor MPU and the direct memory access control unit DMC. The processor MPU processes the switching of the data buffer area in the write/read memory RAM in real time, and uses the direct memory access unit to resume data transfer.
Instruct DMA. As a result, the direct memory access unit DMA starts data transfer to a new data buffer area. On the other hand, the bus control unit BCU, which requires data transfer from the processor MPU to the line control unit LCU, directly transmits a memory access request to the bus interface control unit BIC via the signal line S1. The bus interface control unit BIC, which has received the direct memory access request, transmits the direct memory access request to the direct memory access control unit DMC. Direct memory access control unit
DMC is a direct memory access unit DMA as mentioned above.
If a direct memory access request from the bus interface controller BIC is selected, the controller instructs the bus interface controller BIC to start direct memory access in the same way as described above. At the same time, the internal processing of the processor MPU is temporarily interrupted via the clock control unit CLC. Direct memory access control unit DMC
Bus interface control unit that received instructions from
The BIC directly transmits the memory access permission to the bus control unit BCU (not shown in FIG. 3) via the signal line S2. The bus control unit BCU that received the direct memory access permission accesses the main control unit via the bus B and the bus interface control unit BIC.
Memory RAM that writes and reads data from the MCU
The data is transferred to a predetermined data buffer area within. Note that when such a direct memory access request from the bus control unit BCU arrives while the processor MPU is in the process of switching the ether buffer area in the write/read memory RAM, the processor MPU directly accesses the memory from the bus control unit BCU.
Since it is not possible to control the data buffer area, the switching process of the data buffer area is interrupted, and during this time, the data of the packets arriving from line L are discarded without being accumulated in the read/write memory RAM, and the retransmission of the packets is requested. This may cause inconveniences such as

As is clear from the above explanation, in the conventional line control unit LCU, during processing, it was not possible to reject a direct memory access request from the bus control unit BCU, so the write/read memory
Processing by the processor MPU that requires real-time processing, such as switching processing of data buffer areas in RAM, is interrupted, and as a result, packet data arriving from line L is discarded, and data transfer efficiency is reduced due to packet retransmission processing, etc. There was a fear that he might do it.

(d) Object of the Invention An object of the present invention is to eliminate the drawbacks of the conventional line control unit as described above, and to provide a system in which real-time processing in the line control unit is interrupted by a direct memory access request from the bus control unit. By providing a means for preventing this, the efficiency of data transfer with the main control section can be improved.

(e) Structure of the Invention The purpose of this invention is to provide a circuit URT connected to a line L for transmitting and receiving serial data, and a plurality of line controls that sequentially write received data to a buffer RAM and transfer it to the main control unit as a block on the buffer. a main control unit MCU that performs exchange processing based on the address information of the data block from the line control unit and transfers the processed data block to the line control unit; It consists of a bus control unit BCU that transfers data blocks in bytes between the internal buffer and the buffer memory in the main control unit, and the line control unit temporarily suspends internal processing in response to a request from the bus control unit based on instructions from the main control unit. In a data exchanger that transfers data by performing direct memory access between the main control unit and the buffer RAM of each of the plurality of line control units, configures a predetermined frame, and processes the exchange,
A register CTR is provided in the line control unit LCU to set whether or not to accept direct memory access requests from the bus control unit, and when the line control unit performs processing that requires real-time performance, the register CTR is set to accept or disable direct memory access requests from the bus control unit. If this is set to "no" and normal exchange processing is performed, this is achieved by setting the register to "acceptable" and controlling data transfer to configure a predetermined frame.

That is, in the present invention, the line control unit that executes real-time processing can reject direct memory access requests from the bus control unit by setting information that rejects direct memory access requests in the register. , interruption of real-time processing during processing is prevented.

(f) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings. FIG. 4 is a diagram showing a line control section according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. The line control unit of the embodiment shown in _FIG . , a control register CTR that sets control information that determines acceptance/rejection, and a gate G that ANDs its output and the output of the bus interface control unit BIC.
and is provided. and data buffer
RAM is used for each of the multiple line control units LUC and the main control unit.
Each is built into the MCU. In Figure 4,
Control register CTR usually contains information that allows direct memory access. In this state, the gate G is in a conductive state, and the bus interface control unit BIC, which has received a direct memory access request via the signal line S1 from the bus control unit BCU (not shown), requests the direct memory access control unit DMC to directly access the memory. Access requests can be communicated. On the other hand, the processor that received the data buffer area full notification from the direct memory access unit DMA
The MPU sets information to reject a direct memory access request in the control register CTR. In such a state, the gate G is in a blocking state, and the bus control unit BCU
The bus interface control unit BIC receives a direct memory access request from via the signal line S1.
A direct memory access request cannot be transmitted to the direct memory access control unit DMC. As a result, the direct memory access control section DMC is controlled by the clock control section.
The real-time processing of the processor MPU is not interrupted via the CLC, and memory access permission is not directly transmitted from the bus interface control unit BIC to the bus control unit BCU.
BCU does not start data transfer to line control unit LCU. When the data buffer area switching process of the processor MPU is completed, the processor MPU sets information that allows a direct memory access request in the control register CTR. As a result, the gate G becomes conductive, and from now on, the bus interface control unit BIC
A direct memory access request from is also transmitted to the direct memory access control unit DMC via gate G.
The bus control unit BCU can transfer data to the line control unit LCU.

As is clear from the above description, according to this embodiment, the processor MPU also accepts direct memory access requests from the bus control unit BCU by setting information in the control register CTR to determine whether or not to accept direct memory access requests. Rejection is possible during data buffer area switching processing, eliminating the possibility that packet data will be discarded.

Note that FIG. 4 is only one embodiment of the present invention, and for example, the real-time processing executed by the processor MPU is not limited to data buffer area switching processing, and many other modifications may be considered. However, in either case, the effects of the present invention remain the same. Furthermore, the configuration of the line control unit LCU is not limited to what is shown in the diagram, and many other modifications may be considered.
In either case, the effects of the present invention remain the same. Furthermore, it goes without saying that the data processing apparatus to which the present invention is applied is not limited to the illustrated packet processing apparatus.

(g) Effects of the Invention As described above, according to the present invention, in the data processing device, real-time processing in the line control unit is prevented from being interrupted by a direct memory access request from the bus control unit. The data transfer efficiency of the data processing device is improved.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating an example of a data processing device to which the present invention is applied, FIG. 2 is a diagram illustrating the structure of a packet in FIG. 1, and FIG. 3 is a diagram illustrating an example of a conventional line control unit. FIG. 4 is a diagram showing a line control section according to an embodiment of the present invention. In the figure, A is the address section, B is the bus,
BCU is a bus control unit, BIC is a bus interface control unit, C is a control unit, CLC is a clock control unit,
CTR is a control register, DMA is a direct memory access section, DMC is a direct memory access control section, F is a flag sequence, FCS is a frame check sequence, G is a gate, I is an information section, L is a line,
LCU is line control unit, MCU is main control unit, MPU is processor, RAM is read/write memory,
ROM is a read-only memory, S1 and S2 are signal lines, and URT is a transmitter/receiver.

Claims (1)

[Scope of Claims] 1. A circuit URT connected to line L and transmitting and receiving serial data, and a plurality of line control units LCU that sequentially write received data into a buffer RAM and transfer it to the main control unit as a block on the buffer. A main control unit MCU performs exchange processing based on the address information of the data block from the line control unit and transfers the processed data block to the line control unit; It consists of a bus control unit BCU that transfers data blocks in bytes between buffer memories in the control unit, and the line control unit temporarily interrupts internal processing in response to a request from the bus control unit based on instructions from the main control unit. Each buffer of multiple line control units
In a data exchange device that transfers data by direct memory access between RAMs, configures a predetermined frame, and processes the exchange, the line control unit LCU has a function that responds to a direct memory access request from the bus control unit. A register CTR is provided to set acceptance/disapproval, and when the line control unit is performing processing that requires real-time processing, acceptance/denial is set in this register, and when normal exchange processing is being performed, it is set in this register. A data transfer method characterized by configuring a predetermined frame by setting acceptability and controlling data transfer.