GB1604550A - Method for forming an integrated circuit and an integrated circuit formed by the method - Google Patents
Method for forming an integrated circuit and an integrated circuit formed by the method Download PDFInfo
- Publication number
- GB1604550A GB1604550A GB24485/78A GB2448578A GB1604550A GB 1604550 A GB1604550 A GB 1604550A GB 24485/78 A GB24485/78 A GB 24485/78A GB 2448578 A GB2448578 A GB 2448578A GB 1604550 A GB1604550 A GB 1604550A
- Authority
- GB
- United Kingdom
- Prior art keywords
- region
- grid
- basic
- basic cells
- overlie
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US80190777A | 1977-05-31 | 1977-05-31 | |
| US84747877A | 1977-11-01 | 1977-11-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1604550A true GB1604550A (en) | 1981-12-09 |
Family
ID=27122394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB24485/78A Expired GB1604550A (en) | 1977-05-31 | 1978-05-30 | Method for forming an integrated circuit and an integrated circuit formed by the method |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS54116186A (enrdf_load_stackoverflow) |
| CA (1) | CA1106980A (enrdf_load_stackoverflow) |
| DE (1) | DE2823555A1 (enrdf_load_stackoverflow) |
| FR (1) | FR2393427A1 (enrdf_load_stackoverflow) |
| GB (1) | GB1604550A (enrdf_load_stackoverflow) |
| NL (1) | NL185431C (enrdf_load_stackoverflow) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4295149A (en) * | 1978-12-29 | 1981-10-13 | International Business Machines Corporation | Master image chip organization technique or method |
| FR2495834A1 (fr) * | 1980-12-05 | 1982-06-11 | Cii Honeywell Bull | Dispositif a circuits integres de haute densite |
| US4377849A (en) * | 1980-12-29 | 1983-03-22 | International Business Machines Corporation | Macro assembler process for automated circuit design |
| JPS5832445A (ja) * | 1981-08-20 | 1983-02-25 | Nec Corp | 集積回路装置及びその製造方法 |
| JPS5857749A (ja) * | 1981-10-01 | 1983-04-06 | Seiko Epson Corp | 半導体装置 |
| JPS5890758A (ja) * | 1981-11-25 | 1983-05-30 | Mitsubishi Electric Corp | 相補形集積回路装置 |
| JPS58111347A (ja) * | 1981-12-24 | 1983-07-02 | Matsushita Electric Ind Co Ltd | 半導体装置 |
| JPH0669142B2 (ja) * | 1983-04-15 | 1994-08-31 | 株式会社日立製作所 | 半導体集積回路装置 |
| US4737836A (en) * | 1983-12-30 | 1988-04-12 | International Business Machines Corporation | VLSI integrated circuit having parallel bonding areas |
| JPH0758761B2 (ja) * | 1983-12-30 | 1995-06-21 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 半導体集積回路チップ |
| KR910005605B1 (en) * | 1987-06-08 | 1991-07-31 | Fujitsu Ltd | Master-slice type semiconductor device imbeded multi gate |
| JP5552775B2 (ja) | 2009-08-28 | 2014-07-16 | ソニー株式会社 | 半導体集積回路 |
| JP7004038B2 (ja) * | 2020-07-28 | 2022-01-21 | ソニーグループ株式会社 | 半導体集積回路 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3983619A (en) * | 1968-01-26 | 1976-10-05 | Hitachi, Ltd. | Large scale integrated circuit array of unit cells and method of manufacturing same |
| JPS492796B1 (enrdf_load_stackoverflow) * | 1969-02-28 | 1974-01-22 | ||
| NL176029C (nl) * | 1973-02-01 | 1985-02-01 | Philips Nv | Geintegreerde logische schakeling met komplementaire transistoren. |
| GB1440512A (en) * | 1973-04-30 | 1976-06-23 | Rca Corp | Universal array using complementary transistors |
| JPS50134385A (enrdf_load_stackoverflow) * | 1974-04-09 | 1975-10-24 | ||
| CA1024661A (en) * | 1974-06-26 | 1978-01-17 | International Business Machines Corporation | Wireable planar integrated circuit chip structure |
| US3999214A (en) * | 1974-06-26 | 1976-12-21 | Ibm Corporation | Wireable planar integrated circuit chip structure |
| JPS5816176Y2 (ja) * | 1976-07-16 | 1983-04-01 | 三洋電機株式会社 | 大規模集積回路装置 |
-
1978
- 1978-05-30 GB GB24485/78A patent/GB1604550A/en not_active Expired
- 1978-05-30 NL NLAANVRAGE7805833,A patent/NL185431C/xx not_active IP Right Cessation
- 1978-05-30 DE DE19782823555 patent/DE2823555A1/de not_active Ceased
- 1978-05-31 JP JP6443478A patent/JPS54116186A/ja active Granted
- 1978-05-31 FR FR7816275A patent/FR2393427A1/fr active Granted
- 1978-05-31 CA CA304,470A patent/CA1106980A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2823555A1 (de) | 1978-12-07 |
| CA1106980A (en) | 1981-08-11 |
| FR2393427A1 (fr) | 1978-12-29 |
| NL185431B (nl) | 1989-11-01 |
| NL7805833A (nl) | 1978-12-04 |
| JPH0113222B2 (enrdf_load_stackoverflow) | 1989-03-03 |
| NL185431C (nl) | 1990-04-02 |
| FR2393427B1 (enrdf_load_stackoverflow) | 1983-09-09 |
| JPS54116186A (en) | 1979-09-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PE20 | Patent expired after termination of 20 years |
Effective date: 19980529 |