GB1604550A

GB1604550A - Method for forming an integrated circuit and an integrated circuit formed by the method

Info

Publication number: GB1604550A
Application number: GB2448578A
Authority: GB
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 1977-05-31
Filing date: 1978-05-30
Publication date: 1981-12-09
Also published as: NL7805833A; NL185431C; CA1106980A; NL185431B; FR2393427B1; JPS54116186A; DE2823555A1; FR2393427A1; JPH0113222B2

Description

(54) METHOD FOR FORMING AN INTEGRATED CIRCUIT AND AN INTEGRATED CIRCUIT FORMED BY THE METHOD (71) We, FUJITSU LIMITED, a Japanese Company, of 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention relates to a method of forming an integrated circuit and an integrated circuit formed by the method.

Integrated circuits have heretofore been provided which have been characterised by utilizing large scale integration (LSI). However, the utilization of LSI has several limitations. Although LSI has greatly reduced the cost per unit of logic circuits, there is still a great need to reduce further the cost of such logic circuits. In addition, there is a need to increase the speed at which the active devices in the integrated circuits communicate with each other. There is, therefore, a need for developing a larger scale LSI which, for example, can be called very large scale integration that can be utilized to implement these requirements.

It is an object of the present invention to provide a method for producing an integrated circuit which utilizes basic cells having a plurality of active elements therein which enables the manufacture of a circuit meeting the above mentioned requirements.

According to the present invention there is provided a method for forming an integrated circuit upon the surface of a semiconductor body wherein a plurality of grid points are defined on said semi-conductor surface, each grid point defining a point of intersection between one of a plurality of parallel first grid lines and one of a plurality of parallel second grid lines, the first grid lines being spaced apart by a first dimension and extending parallel to a first axis and the second grid lines being spaced apart by a second dimension and extending parallel to a second axis which is inclined to the first, a plurality of basic cells are formed in the semi-conductor body, each basic cell being selected from a limited number of different designs of basic cell each of which designs is adapted to provide a different logic circuit, at least two different basic cells being selected, and each selected cell being disposed within an area of the semiconductor body surface in the shape of a parellelogram which is not greater than a predetermined area and which includes within its boundaries a plurality of said grid points, each basic cell having formed therein a plurality of active elements and a ground bus, a power bus, an input lead and an output lead connected to the active elements of the basic cell, and a plurality of said basic cells are interconnected to form the intergrated circuit.

Preferably the said axes are arranged to be mutually perpendicular, and said area in the shape of a parallelogram is rectangular.

Preferably the input leads and the power and ground buses extend at right angles with respect to each other.

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. Ia is a top plan view of a basic cell forming part of an integrated circuit embodying the present invention which comprises an inverter; Fig. 1 b is a cross-sectional view taken along the line Ib--lb of Fig. Ia; Fig. Ic is a logic diagram of the inverter shown in Fig. la; Fig. Id is a cross-sectional view taken along the line Id Id of Fig. Ia; Fig. Ie is a circuit diagram showing the two CMOS transistors which make up the inverter shown in Figs. Ia, Ib and Ic; Fig. 2a is a top plan view of another basic cell forming part of an integrated circuit embodying the present invention comprising a two input NAND gate and Fig. 2b shows the logic diagram thereof; Fig. 3a is a top plan view of another basic cell which consists of a two input two-wide AND-OR-INVERTER and Fig. 3b shows the logic diagram thereof; Fig. 4a is a top plan view of a unit cell of the integrated circuit of the present invention which consists of a two input exclusive OR gate which is comprised of the two types of basic cells shown in Figs. I and 3; Fig. 4b is a block diagram of the unit cell shown in Fig. 4a; Fig. 4c is a cross-sectional view taken along the line 4c--4e of Fig. 4a; Fig. 5a is a plan view of another unit cell which serves as an arithmetic and logic unit (ALU) for even bits; Fig. 5b is a block diagram of the unit cell shown in Fig. 5a; Fig. Sc is a cross-sectional view taken along the line 5c--5e of Fig. 5a; Fig. 6a is a plan view of the physical layout of a four bit ALU which may be identified as a functional block in which certain portions have been broken away; Fig. 6b is a block diagram of the four bit ALU shown in Fig. 6a; Fig. 7 is a block diagram of an eight bit ALU; Fig. 8 is a simplified block diagram of an integrated circuit embodying the present invention showing the highest level in the hierarchy.

An integrated circuit embodying the present invention will now be described with reference to Figs. 14 of the drawings. In Fig. la, there is shown a plan view of a basic cell which is one of seven basic cells which may be utilized in the integrated circuit. The basic cell which is shown in Fig. la may be identified as basic cell BCI. The seven basic cells utilized in the integrated circuit consist of the following: BC1 Inverter BC2 2 Input NAND BC3 3 Input NAND BC4 4InputNAND BC5 2 Input 2 Wide AND-OR Inverter BC6 2 Input NOR BC7 Transmission gate Basic cells BC2 and BC5 are shown in Figs.

2a and 3a, respectively, to show the general manner of construction utilized in the basic cells. Basic cells BC3, 4, 6 and 7 have not been shown because with the teaching herein disclosed, one skilled in the art would have no difficulty in fabricating the same. The basic cells BC1 through BC7 constitute the lowest order elements which are utilized in the hierarchy which is involved in fabricating a cellular integrated circuit of the present invention and are utilized as building blocks in the integrated circuit as hereinafter described. All of the basic cells are fabricated in a semiconductor wafer 11 of conventional type. For example, a silicon semiconductor wafer of either a three-inch or four-inch diameter is preferably used in order to make possible the fabrication of an extremely large scale integrated circuit.

It is possible to utilize the herein described integrated circuit design and the hierarchical method also herein described in conjunction with different types of circuitry and/or devices. At this point in time, there are three types of circuits or devices which are particularly adapted to the integrated circuit and method of the present invention which can be identified as complimentary metal oxide semiconductor (CMOS), N channel MOS (NMOS) and I2L. As is well know to those skilled in the art, 12L is bipolar circuitry whereas CMOS and NMOS are both MOS types of circuitry.

In evaluating the different types of circuits, it was found that the various types of circuits had various trade offs against one another. In analysing the circuits it was found that a CMOS requires approximately 1.3 times the amount of transistors that an NMOS does to build the same functional block. In CMOS, there are wiring restrictions which require that almost all of the corresponding gates of N channel transistors and P channel transistors be connected together (except the transmission gate) and that all of the corresponding drains of the N channel transistors and the P channel transistors should be connected together by conductors to obtain the output node.

In the case of NMOS, the gates of the load transistors should be connected to the output node. This is not a severe restriction because the output node can be connected with the polysilicon layer and the diffusion layer or the aluminum layer.

In comparing the processing steps between CMOS and NMOS, approximately two more steps were required for CMOS than NMOS with the same number of masks being required.

In analysing other features of the various circuits, it was found that the CMOS gates have several advantageous DC characteristics. The CMOS gates or inverters provide more noise immunity than NMOS. With CMOS excellent current sourcing capabilities can be obtained. In addition the P channel load transistors operate in the open drain mode which is more effective than the source follower mode in the case of the NMOS load transistor. The DC function of the CMOS circuit is not influenced by changes in the power supply voltage. CMOS gates have the advantage of small power consumption because of the negative standby requirement. This is a particularly important feature where a system is designed in which the probability for the device to operate is small as for example less than 15%. CMOS gates are superior to NMOS gates when the clock rate of the system is relatively slow in comparison with the intrinsic gate switching speed.

In logic implementation and in circuit design, the CMOS circuitry is advantageous because it is not necessary to compensate for the "on" voltage level. It is easy to balance the rise time and the fall time. In addition it makes it possible to utilize a low "on" and high "off' impedance transmission gate. In NMOS circuitry, the circuitry can be made with fewer transistors than CMOS. In the case of circuit density, the NMOS is superior to CMOS but on the other hand the device area occupied by CMOS and NMOS is approximately the same. However, in the case of simple gates, the CMOS gate may occupy as much as 1.6 times the area of an NMOS gate. Weighing all of the various considerations, CMOS circuitry and devices have been utilized in the embodiment of the invention shown in the drawings.

The general construction and fabrication of CMOS devices is well known to those skilled in the art and therefore will not be described in detail.

The number of basic cells has been kept relatively small because in order to achieve maximum flexibility the number of indivisible element i.e. the basic cell should be small.

In connection with the design of the integrated circuit of the present invention it is also desirable to keep the basic cell relatively small in respect of the area which it is to occupy on the wafer. By way of example, it has been found desirable to limit the size of the basic cells such that the largest basic cell would not exceed an area of 9 grid spacings by 6 grid spacings or a total of 54 square grid spaces. This makes it possible to precisely tailor the power inputs for the basic cells. It should be appreciated however that if desired the basic cell can be made larger or smaller without departing from the present invention.

All of the basic cells are designed on a rectangular grid pattern which is defined by horizontal grid markings or lines 12 and vertical grid markings or lines 13 shown in Fig. la lying on X and Y axes respectively.

The scale of the grid markings is arranged in such a manner so that the scale can be increased or decreased to change the size of the grid for purposes hereinafter described.

The spacing between the horizontal grid markings 12 and the vertical grid markings 13 can be the same or different as desired. In the present embodiment, the spacing between the grid markings have the relationship of 8 to 10 with the relationship of 10 corresponding to the spacing between the vertical grid markings 13 and the spacing 8 corresponding to the spacing between the horizontal grid markings 12 for purposes hereinafter described. More specifically the spacing between the vertical grid markings 13 is 10,a and the spacing between the horizontal grid markings 12 is 8.

The grid pattern has also been designed so that each intersection of the grid markings can be established by Cartesian coordinates as for example the Cartesian coordinates in the units shown in Fig. Ia to locate the four corners of the rectangle 14 in which the basic cell is formed. It should be noted that the seven basic cells BC1 through BC7 do not exceed an area of 9 horizontal grid spacings by 6 vertical grid spacings or a total of 54 square grid spaces. However, it should be appreciated that the basic cells need not necessarily have the same geometrical shape.

They can have different rectangular shapes with the only design constraint being that they do not exceed the maximum area of 54 square grid spaces as pointed out above.

Within the rectangle formed on the grid pattern there are also provided a plurality of grid points 16 which are located within the basic cell and which are defined by the intersections of the vertical and horizontal grid markings of the grid pattern. These grid points on intersections of the grid markings 12 and 13 are indicated by crosses 16 as shown in Fig. Ia. The positions of these crosses 16 can be located by Cartesian coordinates. Thus, it can be seen that each basic cell will include within its area certain grid points 16.

Each of the basic cells is provided with two spaced apart and parallel power connections or leads 21 and 22 with the lead 21 being a power lead or bus and lead 22 being a ground lead or bus. It is also provided with one or more input leads and one or more output terminals or leads. Thus, the basic cell shown in Fig. la is provided with at least one input lead 23 and a single output lead 24. It can be seen from the arrangement shown that the ground and power leads extend in a vertical direction whereas the input and the output leads extend in a horizontal direction at right angles to the ground and power buses which intersect in the regions occupied by the basic cells. In the basic cell shown in Fig.

la, it can be seen that the basic cell has a length of9 and a width of3 to provide a basic dimension of 27.

A cross sectional view of the basic cell in Fig. Ia is shown in Fig. Ib. As shown in Fig.

Ib it consists of a conventional CMOS type construction in which a silicon semiconductor body II is doped with an N-type impurity. To provide an N-type region the body II has a surface 27 on which there is deposited a field oxide layer 28. Large openings or windows 29 and 30 are formed in the field oxide layer 28 to expose the surface 27. A P-type well or region 31 is formed by ion implantation in the body I S through the field oxide layer 28 and is defined by a PN junction 32 which extends to the surface 27.

A thin gate oxide layer 33 is grown on the surface 27 in the opening 29. A polycrystalline layer is then formed on the gate oxide layer 33 and etched to provide a polycrystalline gate 34. N + source and drain regions 36 and 37 are implanted using the gate 34 and the field oxide 28 as a mask. A channel region 38 is formed between the source and drain regions 36 and 37 and underlies the gate 34.

A glass layer 39 is deposited on the field oxide layer 28 and into the opening 29.

Contact openings 41 and 42 are formed through the glass layer 39 and the gate oxide layer 33 to expose the surface 27 overlying the source and drain regions 36 and 37. A layer of metallization of a suitable material such as aluminum is provided on the glass layer 39 and extends through openings 41 and 42 to make contact to the source and drain regions 36 and 37 to provide source and drain leads 43 and 44 which also can be identified as the ground bus 22 and the output lead 24 respectively.

Another cross sectional view of the basic cell in Fig. la is shown in Fig. I ld As shown in Fig. Id the P-type well 31 is defined by the PN junction 32 which extends to the surface 27 between the openings 29 and 30. The opening 30 is for making a P channel transistor element. P-type source region and drain region 40 are also formed by ion implantation using the polycrystalline gate and the field oxide 28 as a mask.

In Fig. Ia, the output lead 24 is within the interior of the rectangle 14. Access to the output lead 24 can be readily obtained by providing a second layer of insulating material (not shown) forming a hole through the second layer of insulating material to the output pad or lead 24 and forming a second layer of metallization on the second layer of insulating material to form a connection to the hole. Access can also be obtained through a hole between the first layer metallization and the drain region 37 as shown in Figs. 4a, 5a and 6a and as hereinafter described. Because CMOS circuitry is being utilized, the leads can be relatively thin, particularly since there is minimal static power consumption by the circuit. In other words there is not standby power requirement.

With the arrangement shown it can be seen that all of the crucial parts of the circuitry of the basic cell are laid out in such a manner that they overlie grid points 16.

This is true in respect to the power and ground buses 21 and 22 and the output lead 24. Placing the output lead 24 within the interior of the rectangular area gives flexibility in the interconnection of the basic cells to form a unit cell and other larger integrated circuits as hereinafter described.

Fig. Ie is a circuit diagram of the inverter shown in Figs. Ia, Ib, Ic and Id and shows that the inverter consists of two complimentary N channel and P channel CMOS transistors.

In Figs. 2a and 2b there is shown a two input NAND gate which utilizes the same basic geometry as the basic cell in Fig. Ia. As can be seen, the rectangle 51 which is utilized for the basic cell BC2 is larger than the rectangle 14 of the basic cell By 1. From the Cartesian coordinates provided it can be seen that the rectangle has a length of 9 and a width of 4 to provide a total area of 36. The same single power and ground buses 21 and.

22 are provided. Two spaced apart and parallel horizontal input leads 52 and 53 are provided and an output lead 54. The inputs have also been labelled with the numbers 1 and 2 and the output with number 3. From examination of Fig. 2a it can be seen that the same type of organisation it utilized in the basic cell BC2 as in the basic cell BCI.

In Figs. 3a and 3b there is shown a two input two-wide AND-OR-INVERTER. A still latger rectangle 56 is provided for this basic cell BC5 which has again a length of 9 and a width of 6 for a total area of 54. Again, vertical power and ground buses 21 and 22 are provided. Four separate spaced apart parallel and horizontal input leads 57 are provided which are numbered I through 4 as shown. An output lead or bus 58 is provided which has been numbered 5.

From each of the three basic cells hereinbefore described, a single power bus and a single ground bus are provided for each basic cell which extend in a vertical direction at right angles to the input buses and intersect therewith as shown in the drawings.

It should be appreciated that although in each case so far described the output leads have been shown within the interior of the basic cells, if desired, it is possible to place the input and output connections for the basic cells near the outer perimeters of the basic cells. However, this has a disadvantage in that it makes the basic cell larger than when the output is placed within the interior of the rectangular basic cell. It should be noted with respect to the basic cells which are shown in Figs. Ia, 2a, and 3a that there are areas in the basic cells between the inputs and on the right and left hand sides as viewed in the drawings which can be utilized as connection areas through which connections can be made directly to the sources and drains by forming holes through the insulating layers overlying the same.

In Figs. 4a and 4b there is shown the construction of a unit cell UC7 which is the next higher level in the hierarchy utilized in connection with the present integrated circuit design. The unit cell is comprised of a plurality of basic cells. It can be seen, the unit cell UC7 shown in Fig. 4a uses a considerably larger rectangle 61 which has a dimension of 11 in one direction and 9 in another for a total area of 99. The spacings between the horizontal grid lines and vertical grid lines represent 10 microns and 8 microns, respectively, and this would represent a distance of 88 microns in one direction and 90 microns in another direction.

From Fig. 4a it can be seen that the various basic cells utilized in the unit cell UC7 use the same power bus 21 and the same ground bus 22. Two inputs 62 which have been provided have been identified with the numerals 1 and 2. In addition, three output leads 63 have been provided which carry the numerals 3, 4, and 5. When the designations X and Y are utilized, this indicates that the basic cell has been flipped or turned over with respect to the horizontal axis, the X axis, or the vertical axis, the Y axis, respectively. Thus, generally speaking there are four basic positions for each basic cell, of which one is the position shown in Fig. la, a second is when it is flipped about the X or horizontal axis, a third position is obtained by flipping about the Y or vertical axis and a fourth is obtained by flipping about both the X and Y axis which is equivalent to rotating the entire cell by 180 degrees.

Being able to flip the basic cells is advantageous because it makes it possible to share some regions in the basic cells. When a region can be shared, the two combined regions will take less area than two separate regions. More specifically the upper small rectangles 64 and 75 comprise two basic cells I(BC-I) and 2(BC-lx). The basic cells l(BC I ) and 2(BC-lx) are the same as the basic cell BCI except the basic cell l(BC-I) has an origin of (1,6) in the rectangular area 61 and the basic cell 2(BC-lx) in the lower portions of the rectangles 64 and 75 has an origin of (1.8) and is turned or flipped over with respect to the X axis. Furthermore, it should be noted that the basic cells l(BC-l) and 2(BC-lx) share a single source area 66 for N channel transistors to be formed in the small rectangle 64 and share a single source area 67 for P channel transistors to be formed in the small rectangle 65. For this reason the basic cell 2(BC-lx) has been flipped or turned over The basic cell 3(BC-5x) in the lower portion of the area 61 is turned over to avoid an intersection of the output leads 3 and 5. It is more advantageous to make a single P-type well or region rather than two separate Ptype wells in the semiconductor body.

Referring to Fig. 4c there is shown a cross sectional view along the line 4c of the unit cell UC7 of Fig. 4a. In Fig. 4c a P-type well region 68 is formed by the procedure described above to make it small. Basically each basic cell requires one P-type well thereby eniarging the required cell area.

According to the present embodiment of the invention, a single P-type well is formed which has provided therein all N channel transistor areas of each basic cell. The PN junction 69 ends at the surface of the semiconductor body and determines the boundary of the P-type well 68. The other portions of the active devices, the transistors, are not described because they are the same as in the previous embodiments hereinbefore described.

In Figs. 5a and 5b there is shown the physical layout and the logic diagram of an arithmetic and logic unit (ALU) which is a one bit (even bit) ALU which may be identified as unit cell UC16. The unit shown has four mode control inputs. The unit can make arithmetic and logical operations such as addition, subtraction and logical AND, NOR, etc.

As can be seen the ALU as shown in Fig.

5a is formed in a rectangle 71 which is 22 units wide along the X axis and 31 units high along the Y axis. Multiplying the units along the X axis by 8 and the units along the Y axis by 10 and utilizing the 8 by 10 system hereinbefore described, gives the total area for the rectangle 71 as 54,560 square microns.

Utilizing Cartesian coordinates the exact location of the UC16 can be ascertained on the wafer. A description of the components which make up the unit cell 16 is shown on the right and left hand sides of the rectangle 71. For example, the first component or basic cell on the right side is identified as l(BC-lx) with Cartesian coordinates of 12 and 31.

These coordinates give the location of the origin of the basic cell. The indication also indicates that the basic cell I has been flipped about the X axis. The origin will then be in the upper left hand corner of the basic cell.

The second component or basic cell is on the left side and is identified as 2(BC-lxy) with Cartesian coordinates of 10 and 31 and with a basic cell flipped about the X and Y axes. The third component is on the right hand side and is identified as 3(BC-5x). It is flipped about the X axis and has its origin at the Cartesian coordinates 12 and 25. As can be seen. each component or basiC cell of the unit cell UC16 has been identified with its coordinates and its orientation with respect X and Y axes. The mode selection lines have been identified as SO, SI, S2, and S3. The numbers 3, 4, 5 and 6 also associated with these mode selection lines are also set forth in Fig. 5b. The other lines have also been identified by additional numbers. The lines 3 to 7 are for metal leads to be formed on an insulating layer. The insulating layer will cover the entire surface of the wafer or semiconductor body to insulate the ground bus, the power bus. the input leads, the output lead and other interconnecting leads from the basic cells.

As can be seen, the components 1, 3,6 and II are flipped about the X axis in the right hand side of the rectangle 71 and the components 2, 4, 5, 8. 10 and 9 are flipped about at least the Y axis in the left hand side of the rectangle 71 so that the same type of circuit elements are closely arranged back-toback with each other. This arrangement results in using one P-type well region including the same type of circuit elements in the rectangle 71.

To clarify this arrangement a cross sectional view of Fig. 5a is shown in Fig. 5c. In Fig. Sc, a single P-type well 72 includes the same type of circuit elements to which ground buses 22R and 22L are oonnected.

The PN junctions 73 between the P-type well 72 and N type wafer extends to the surface of the wafer. The vertical lines shown in Fig. 5a are formed from a suitable metal layer such as aluminum provided on the glass layer 74.

A second glass layer 75 covers the entire surface of the wafer on which the horizontal lines 3 to 7 are formed in the following steps.

In Fig. 6a and 6b there are shown respectively the physical layout and the logic diagram of functional block FB27 which represents a still higher level in the hierarchy and shows a 4-bit ALU. It consists of two unit cells UC 15, two unit cells UC 16 and one basic cell BC I. In Fig. 6b there are shown pin numbers of differing physical sizes. The larger pin numbers are for the functional block whereas the smaller pin numbers are the unit cell pin numbers.

In Fig. 7, there is shown an 8-bit arithmetic/logic unit (ALU). It consists of two FB27's of the type shown in Figs. 6a and 6b. As is also shown it is provided with a carry in lead and a mode control lead as labelled. In addition there are provided ALU control lines as shown which are connected into the FB27's. These ALU control lines determine whether addition or subtraction is performed by the FB's. The mode control lines determines whether an arithmetic or logical operation is to be performed by the ALU as shown in Fig. 7. At the top of each FB shown in Fig. 7 there are provided four A-operand lines and four B-operand lines. Thus, eight inputs are provided for each FB. Four output or result lines are provided for each FB and in addition, each FB is provided with a carry/borrow out line. Use of all these lines is well known to those skilled in the art and therefore will not be described in detail.

In Fig. 8 there is shown a block diagram of a complete system. As shown therein, it consists of four functional blocks, two registers 81 and 82, an ALU 83, and a bus control 84. Data supplied on the input 86 is placed in the registered 81 and 82 and will be added or subtracted in accordance with the ALU control and the results will be placed in either one of the registers 81 or 82 in accordance with the bus control 84.

The block diagram in Fig. 8 in a simplified form characterises the highest level of the system using the hierarchy of the present meth structures of the type described in Figs. 1 through 8 includes a plurality of basic cells formed in the semiconductor body and having an area including a plurality of grid points. Each basic cell has first, second and third regions for making electrical connection to the basic cell. For example, in Fig. ld, the region 40 has its top surface exposed to make contact with the power bus 21 through an opening in the insulating layer 33. In a similar manner, region 36 is exposed through an opening in the insulating layer 33 to make electrical connection to the ground bus 22.

The regions 36 and 40 are located to overlie first and second ones of the plurality of grid points. Those grid points are the same ones which the power bus 21 and the ground bus 22 overlie as shown in Fig. 1 a. The basic cells also have a third region spaced from selected ones of the grid lines so as to be located not to overlie any of the grid points. In Fig. la, for example, the input region 23 is such a third region. Note that the region 23 in Fig. 1 does not overlie any of the grid points 16 but rather is offset therefrom by some predetermined offset. The predetermined offset in Fig. la is approximately equal to one-half the dimension between the grid lines parallel to the X axis. Such a predetermined offset for the third region is significant in that any hole connection made at a grid point does not contact the third region.

The power buses 21 and 22 are examples of conductors which are colinear with the grid markings defining the grid point. While the input region 23 (third region) is located not to overlie the grid points, the relationship between that region and the conductors may be interchanged. For example, the input region 23 may be made colinear with one of the grid markings defining the grid points while one or more of the conductors 21 and 22 may be located with a predetermined offset from a grid marking so as not to overlie any of the grid points. With such an interchange, via holes through the insulating layer do not cause unwanted contact between the conductors and the third region.

Some embodiments disclosed also include a plurality of linear regions or conductors spaced apart from each other by the same spacing as the grid point but having a predetermined offset therefrom. In Fig. 3a, for example, the input regions 57 are such a plurality of regions. None of the regions 57 overlie any of the grid points.

The basic cells discussed in connection with Figs. I through 8 also include a fourth region which serves for making an electrical output connection. The fourth region is conveniently located to overlie grid points.

Additionally, an output conductor, such as conductor 54 in Fig. 2a, located colinear with one or more grid markings may have via hole connections to the fourth region output connection without undesirably contacting the input regions (such as input regions 52 and 53 in Fig. 2a).

WHAT WE CLAIM IS: 1. A method for forming an integrated circuit upon the surface of a semiconductor body wherein a plurality of grid points are defined on said semi-conductor surface, each grid point defining a point of intersection between one of a plurality of parallel first grid lines and one of a plurality of parallel second grid lines, the first grid lines being spaced apart by a first dimension and extending parallel to a first axis and the second grid lines being spaced apart by a second dimension and extending parallel to a second axis which is inclined to the first, a plurality of basic cells are formed in the semiconductor body, each basic cell being selected from a limited number of different designs of basic cell each of which designs is adapted to provide a different logic circuit, at least two different basic cells being selected, and each selected cell being disposed within an area of the semiconductor body surface in the shape of a parellelogram which is no greater than a predetermined area and which includes within its boundaries a plurality of said grid points, each basic cell having formed therein a plurality of active elements and a ground bus, a power bus, an input lead and an output lead connected to the active elements of the basic cell, and a plurality of said basic cells are interconnected to form the integrated circuit.

2. A method according to claim 1, in which said axes are arranged to be mutually perpendicular, and said area in the shape of a parellelogram is rectangular.

3. A method according to claim 2, wherein the input leads and the power and ground buses extend at right angles with respect to each other.

4. A method according to claim 1, 2 or 3, wherein a plurality of the basic cells are connected together so as to define a unit cell, a further plurality of the basic cells are connected together to form at least one other unit cell, and the unit cells are interconnected by means carried by the semiconductor body into a functional block.

5. A method according to claim 4, wherein a plurality of functional blocks are formed and the functional blocks are interconnected by means carried by the semiconductor body into an integrated circuit system.

6. A method according to any preceding claim, wherein the output lead of each basic cell is formed within the area in the shape of a parellelogram of each basic cell in a region which is remote from the outer perimeter of the said area.

7. A method according to any preceding claim, wherein at least a plurality of the basic

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. structures of the type described in Figs. 1 through 8 includes a plurality of basic cells formed in the semiconductor body and having an area including a plurality of grid points. Each basic cell has first, second and third regions for making electrical connection to the basic cell. For example, in Fig. ld, the region 40 has its top surface exposed to make contact with the power bus 21 through an opening in the insulating layer 33. In a similar manner, region 36 is exposed through an opening in the insulating layer 33 to make electrical connection to the ground bus 22. The regions 36 and 40 are located to overlie first and second ones of the plurality of grid points. Those grid points are the same ones which the power bus 21 and the ground bus 22 overlie as shown in Fig. 1 a. The basic cells also have a third region spaced from selected ones of the grid lines so as to be located not to overlie any of the grid points. In Fig. la, for example, the input region 23 is such a third region. Note that the region 23 in Fig. 1 does not overlie any of the grid points 16 but rather is offset therefrom by some predetermined offset. The predetermined offset in Fig. la is approximately equal to one-half the dimension between the grid lines parallel to the X axis. Such a predetermined offset for the third region is significant in that any hole connection made at a grid point does not contact the third region. The power buses 21 and 22 are examples of conductors which are colinear with the grid markings defining the grid point. While the input region 23 (third region) is located not to overlie the grid points, the relationship between that region and the conductors may be interchanged. For example, the input region 23 may be made colinear with one of the grid markings defining the grid points while one or more of the conductors 21 and 22 may be located with a predetermined offset from a grid marking so as not to overlie any of the grid points. With such an interchange, via holes through the insulating layer do not cause unwanted contact between the conductors and the third region. Some embodiments disclosed also include a plurality of linear regions or conductors spaced apart from each other by the same spacing as the grid point but having a predetermined offset therefrom. In Fig. 3a, for example, the input regions 57 are such a plurality of regions. None of the regions 57 overlie any of the grid points. The basic cells discussed in connection with Figs. I through 8 also include a fourth region which serves for making an electrical output connection. The fourth region is conveniently located to overlie grid points. Additionally, an output conductor, such as conductor 54 in Fig. 2a, located colinear with one or more grid markings may have via hole connections to the fourth region output connection without undesirably contacting the input regions (such as input regions 52 and 53 in Fig. 2a). WHAT WE CLAIM IS:

1. A method for forming an integrated circuit upon the surface of a semiconductor body wherein a plurality of grid points are defined on said semi-conductor surface, each grid point defining a point of intersection between one of a plurality of parallel first grid lines and one of a plurality of parallel second grid lines, the first grid lines being spaced apart by a first dimension and extending parallel to a first axis and the second grid lines being spaced apart by a second dimension and extending parallel to a second axis which is inclined to the first, a plurality of basic cells are formed in the semiconductor body, each basic cell being selected from a limited number of different designs of basic cell each of which designs is adapted to provide a different logic circuit, at least two different basic cells being selected, and each selected cell being disposed within an area of the semiconductor body surface in the shape of a parellelogram which is no greater than a predetermined area and which includes within its boundaries a plurality of said grid points, each basic cell having formed therein a plurality of active elements and a ground bus, a power bus, an input lead and an output lead connected to the active elements of the basic cell, and a plurality of said basic cells are interconnected to form the integrated circuit.

cells are of the same design but have patterns which are flipped around at least one of the said axes.

8. A method according to any preceding claim, wherein an insulating layer is formed over said basic cells, the power bus and ground bus are formed on said insulating layer in a spaced apart parallel relationship, the input lead is formed on said insulating material so as to cross said power bus and said ground bus to form input lead intersections therewith. said basic cells, said power bus, and said ground bus being arranged so that at least one input lead intersection overlies each basic cell, the output lead is formed on the said insulating layer. and conducting means are formed which extend from each basic cell through the insulating layer and make electrical connections with said power bus, said ground bus, said input lead and said output lead.

9. A method according to claim 8, wherein a plurality of input leads are formed in a spaced parallel relationship.

10. A method according to claim 8 or 9, wherein interconnecting leads are formed on said insulating layer to interconnect said basic cells to form a larger integrated circuit.

li. A method according to claim 8, 9 or 10, wherein said input leads are formed from polycrystalline silicon.

12. A method according to claim 8, 9, 10 or 11, wherein each said basic cell is formed as a complementary MOS circuit.

13. A method according to any preceding claim, wherein the semiconductor body is of the N type and a P-type well is formed therein, at least portions of at least two basic cells being disposed in said P-type well.

14. A method according to any preceding claim, wherein contact pads for each of said basic cells are formed a predetermined Cartesian coordinates relative to said grid lines, and conducting connections are formed between said contact pads of said basic cells and said power bus, ground bus, said input lead and said output lead.

15. A method according to any preceding claim, wherein said basic cells are selected from circuits comprising an inverter circuit, a NAND circuit, an AND-OR inverter circuit, a NOR circuit and a transmission gate circuit.

16. A method according to claim 1 or 2, wherein each basic cell has first, second, and third regions to which electrical connections are made, the first and second regions being formed so as to overlie first and second ones of said plurality of grid points respectively, and the third region being formed so as not to overlie said grid points, an insulating layer is formed to overlie said basic cells, the insulating layer having openings at selected grid points, and first and second conductors are formed on said insulating layer, said first and second conductors being colinear with first and second ones of said grid lines respectively, extending to overlie said first and second ones of said plurality of grid points respectively, and connecting through openings in said insulating layer to said first and second regions respectively.

17. A method according to claim 16, wherein said first and second conductors are the power and ground buses respectively and are formed so as to extend parallel to said second axis, wherein said third region is an input region arranged parallel to said first axis, and wherein each of said basic cells is formed with a fourth region connected to the output lead.

18. A method according to claim 17, wherein said fourth region is formed over a selected grid point and an additional conductor is formed in line with a grid line so as to overlie said selected grid point and connect through said insulating layer to contact said fourth region at said selected grid point.

19. An integrated circuit according to claim 16, 17 or 18, wherein said third region for each of said basic cells is formed in line with a line parallel to and spaced by a predetermined offset from selected ones of said grid lines parallel to said first axis, said predetermined offset being less than said first dimension.

20. An integrated circuit formed in accordance with the method according to any preceding claim.

21. A method for forming an integrated circuit substantially as hereinbefore described with reference to the accompanying drawings.

22. An integrated circuit substantially as hereinbefore described with reference to the accompanying drawings.