FR2393427A1 - INTEGRATED CELLULAR CIRCUIT AND HIERARCHICAL PROCESS OF REALIZATION - Google Patents

INTEGRATED CELLULAR CIRCUIT AND HIERARCHICAL PROCESS OF REALIZATION

Info

Publication number
FR2393427A1
FR2393427A1 FR7816275A FR7816275A FR2393427A1 FR 2393427 A1 FR2393427 A1 FR 2393427A1 FR 7816275 A FR7816275 A FR 7816275A FR 7816275 A FR7816275 A FR 7816275A FR 2393427 A1 FR2393427 A1 FR 2393427A1
Authority
FR
France
Prior art keywords
realization
hierarchical process
integrated cellular
cellular circuit
basic cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7816275A
Other languages
French (fr)
Other versions
FR2393427B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of FR2393427A1 publication Critical patent/FR2393427A1/en
Application granted granted Critical
Publication of FR2393427B1 publication Critical patent/FR2393427B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un circuit intégré réalisé dans un substrat semi-conducteur. Le substrat porte un quadrillage rectangulaire suivant les axes X et Y. Plusieurs types de cellules de base sont disposées suivant ce quadrillage et sont interconnectées de manière à former des élements logiques. Chaque cellule de base comporte deux lignes d'alimentation et des conducteurs d'entrée et de sortie. L'invention s'applique notamment à la réalisation des calculateurs en circuits intégrés.The invention relates to an integrated circuit produced in a semiconductor substrate. The substrate has a rectangular grid along the X and Y axes. Several basic cell types are arranged along this grid and are interconnected so as to form logical elements. Each basic cell has two power lines and input and output conductors. The invention applies in particular to the production of computers in integrated circuits.

FR7816275A 1977-05-31 1978-05-31 INTEGRATED CELLULAR CIRCUIT AND HIERARCHICAL PROCESS OF REALIZATION Granted FR2393427A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US80190777A 1977-05-31 1977-05-31
US84747877A 1977-11-01 1977-11-01

Publications (2)

Publication Number Publication Date
FR2393427A1 true FR2393427A1 (en) 1978-12-29
FR2393427B1 FR2393427B1 (en) 1983-09-09

Family

ID=27122394

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7816275A Granted FR2393427A1 (en) 1977-05-31 1978-05-31 INTEGRATED CELLULAR CIRCUIT AND HIERARCHICAL PROCESS OF REALIZATION

Country Status (6)

Country Link
JP (1) JPS54116186A (en)
CA (1) CA1106980A (en)
DE (1) DE2823555A1 (en)
FR (1) FR2393427A1 (en)
GB (1) GB1604550A (en)
NL (1) NL185431C (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2495834A1 (en) * 1980-12-05 1982-06-11 Cii Honeywell Bull INTEGRATED CIRCUIT DEVICE OF HIGH DENSITY
EP0080361A2 (en) * 1981-11-25 1983-06-01 Mitsubishi Denki Kabushiki Kaisha Complementary metal-oxide semiconductor integrated circuit device of master slice type
EP0295183A2 (en) * 1987-06-08 1988-12-14 Fujitsu Limited Master slice type semiconductor integrated circuit having sea of gates

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295149A (en) * 1978-12-29 1981-10-13 International Business Machines Corporation Master image chip organization technique or method
US4377849A (en) * 1980-12-29 1983-03-22 International Business Machines Corporation Macro assembler process for automated circuit design
JPS5832445A (en) * 1981-08-20 1983-02-25 Nec Corp Integrated circuit device and manufacture thereof
JPS5857749A (en) * 1981-10-01 1983-04-06 Seiko Epson Corp Semiconductor device
JPS58111347A (en) * 1981-12-24 1983-07-02 Matsushita Electric Ind Co Ltd Semiconductor device
JPH0669142B2 (en) * 1983-04-15 1994-08-31 株式会社日立製作所 Semiconductor integrated circuit device
US4737836A (en) * 1983-12-30 1988-04-12 International Business Machines Corporation VLSI integrated circuit having parallel bonding areas
JPH0758761B2 (en) * 1983-12-30 1995-06-21 インターナショナル・ビジネス・マシーンズ・コーポレーション Semiconductor integrated circuit chip
JP5552775B2 (en) 2009-08-28 2014-07-16 ソニー株式会社 Semiconductor integrated circuit
JP7004038B2 (en) * 2020-07-28 2022-01-21 ソニーグループ株式会社 Semiconductor integrated circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2227638A1 (en) * 1973-04-30 1974-11-22 Rca Corp
FR2276693A1 (en) * 1974-06-26 1976-01-23 Ibm MICROPLATE STRUCTURE OF INTEGRATED CIRCUITS AND ITS MANUFACTURING PROCESS
US3983619A (en) * 1968-01-26 1976-10-05 Hitachi, Ltd. Large scale integrated circuit array of unit cells and method of manufacturing same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492796B1 (en) * 1969-02-28 1974-01-22
NL176029C (en) * 1973-02-01 1985-02-01 Philips Nv INTEGRATED LOGIC CIRCUIT WITH COMPLEMENTARY TRANSISTORS.
JPS50134385A (en) * 1974-04-09 1975-10-24
JPS5314469B2 (en) * 1974-05-17 1978-05-17
US3999214A (en) * 1974-06-26 1976-12-21 Ibm Corporation Wireable planar integrated circuit chip structure
JPS5816176Y2 (en) * 1976-07-16 1983-04-01 三洋電機株式会社 Large scale integrated circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983619A (en) * 1968-01-26 1976-10-05 Hitachi, Ltd. Large scale integrated circuit array of unit cells and method of manufacturing same
FR2227638A1 (en) * 1973-04-30 1974-11-22 Rca Corp
FR2276693A1 (en) * 1974-06-26 1976-01-23 Ibm MICROPLATE STRUCTURE OF INTEGRATED CIRCUITS AND ITS MANUFACTURING PROCESS

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/77 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2495834A1 (en) * 1980-12-05 1982-06-11 Cii Honeywell Bull INTEGRATED CIRCUIT DEVICE OF HIGH DENSITY
EP0080361A2 (en) * 1981-11-25 1983-06-01 Mitsubishi Denki Kabushiki Kaisha Complementary metal-oxide semiconductor integrated circuit device of master slice type
EP0080361A3 (en) * 1981-11-25 1985-01-16 Mitsubishi Denki Kabushiki Kaisha Complementary metal-oxide semiconductor integrated circuit device of master slice type
EP0295183A2 (en) * 1987-06-08 1988-12-14 Fujitsu Limited Master slice type semiconductor integrated circuit having sea of gates
EP0295183A3 (en) * 1987-06-08 1990-07-11 Fujitsu Limited Master slice type semiconductor integrated circuit having sea of gates

Also Published As

Publication number Publication date
FR2393427B1 (en) 1983-09-09
NL7805833A (en) 1978-12-04
JPH0113222B2 (en) 1989-03-03
CA1106980A (en) 1981-08-11
DE2823555A1 (en) 1978-12-07
JPS54116186A (en) 1979-09-10
NL185431B (en) 1989-11-01
GB1604550A (en) 1981-12-09
NL185431C (en) 1990-04-02

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