JPS5857749A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent short-circuit of wirings and contraction of size during the photolithographic process due to reflection of light by enlarging apertures to be provided at the field oxide film in the direction of wiring adjacent to gate electrodes. CONSTITUTION:When the gate aperture 23 is enlarged in both directions of wirings 24, 26 running adjacent to the gate electrode 25, the wirings 24, 26 in both sides do not overlap with the tapered partion of the field oxide film 22 in the periphery of the gate aperture. According to this structure, the wiring is not short-circuitted or does not become narrow due to sensitization of resist by the reflected light in the photolithographic process at the time of forming metal wirings. The light reflected by the tapered portion of the field oxide film 22 can be absorbed within the resist by opening an aperture on the area extending from the center of adjacent wiring to the outside thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a metal gate 7-alpha line type MO8 semiconductor device I.
There is something about the shape of the gate opening row t'.

Traditionally, source and drain II
The transistor of the metal gate self-alignment type Motif semiconductor device forming the pin had a structure as shown in the top view of FIG. 1 and the cross-sectional view of FIG. 2.

First, a source 2 and a drain 5 are formed on the semiconductor substrate M11 by thermal diffusion, and then field oxidation 1111 is formed, a gate opening 4 is formed in a portion that will become a transistor, and gate oxidation is performed to form a gate oxide film 13. After that, metal interconnections @5, 6.7 are formed. The gate electrode of the gate opening 4 is the wiring 6, and the wiring 5 and 7 formed parallel to the wiring 6 are also formed with gate openings 8.9 in necessary parts, forming part of the transistor. Thereafter, ions are implanted into necessary portions through the gate oxide film in the gate opening to form an implanted diffusion layer 10, thereby forming the source 2. Channel part KI for drain 3! The wired transistor is completed.

In this way, after metal wiring is formed, ions are implanted through the gate opening to connect with the already formed diffusion layer, so the gate opening needs to be opened near the adjacent metal wiring as shown in Figure 1. There is.

Therefore, for example, if the mask alignment deviates, #E
As shown in FIG. 2, a portion of the wiring 5' that is in contact with the tapered portion 12 of the field oxide film extending around the outer periphery of the gate opening becomes overhanging.

In such a state, as shown in FIG. 3, during photolithography of the wiring, the arrow 190 is
When a negative resist is used, the resist between the resist patterns 15 and 16, which will become the wiring, is exposed to light and remains in a pattern of 180, and after the metal layer is etched, the pattern between the metal wirings is formed. Zuru Yasu. I was. ＼When using a positive resist, the game 11 is caused by the reflection of light, similar to KFi.
The problem was caused by fine sand.

The present invention eliminates such drawbacks. The gate opening formed in the field oxide 11 is used as the gate electrode.
If the wiring method is enlarged, it will solve the problem caused by the reflection of light on the front panel. Hereinafter, embodiments of the present invention will be described with reference to a top view of Figure 4 and a sectional view of Figure 5.

First, the shisome 2 is placed on the N-type silicon substrate 28 by a known method.
0, a PTJJ thermal diffusion layer for the drain 21 is formed as shown in Fig. 5, and a field oxidation layer 22 is first formed. A gate opening 23 is formed by this field-forming MK photolithography process, and gate oxide #29 is formed in the opening. After further forming a metal layer m 2 ' 125.26 1.
In the present invention, a cell line ion implantation layer 27 is formed by ion implantation of boron ions to form a transistor. In the present invention, as shown in FIGS. By enlarging the gate opening in both directions of 26, it is possible to eliminate the taper part K on both sides of the gate opening.

As shown in FIG. 4, in the structure of the present invention, the gate voltage 25 is I! 1
The arrangement m24.26 of iIII has the same flat rMK as the gate electrode 25, and the taper part of the field film does not overlap with K, so it is different from the conventional fl! There is no thinning of the wiring sheet due to the reflection of light during the photolithography process used to form metal wiring.

Note that with the gate structure according to the present invention, the current consumption increases due to the increase in wiring capacitance, but when adjusted to 1.81 for a typical low current consumption clock, the increase is within 5 hours of the conventional one. There is no particular problem.

In addition, in the embodiment, the gate opening was explained as being formed outside the wiring adjacent to the gate electrical contact. The effects of the present invention are achieved by absorption within the resist.

A simple explanation of twm Figure 1: A top view of a conventional MOB type transistor Figure 2: A conventional MO! 1 showing Ill transistor
IliI1 Figure 3...Cross-sectional view showing conventional MQ811) Runsister 1...Double oxide film 2...Source 5 by thermal diffusion...Drain 4 by thermal diffusion...Gate opening 5...Metal wiring 6...・Gate electrode 7 ・・Metal wiring 8 ・・Gate opening 9 ・・Gate opening 10 ・・Diffusion layer 11 by ion implantation ・・Semiconductor substrate 12 ・・Tapered surface of gate opening 15 ・・Gate identification film 14 ...E) Metal layer 15 before IJ treatment...Resist pattern 16 of wiring...Resist pattern 17 of gate electrode...Resist pattern 18 of interconnection...Resist pattern 19 caused by reflection of light on tapered surface...Light Figure 4: Top view showing the gate opening according to the present invention Figure 5: Side view showing the gate opening according to the present invention 20 Source 21 by thermal diffusion Drain 22 by thermal diffusion Field Oxide film 23...Gate opening 24...Metal wiring 25...
Gate electrode 26...Metal wiring 27...Selfaline mineral dispersion layer by ion implantation AK 28...Silicon substrate 29...Gate oxide film and above Supplier: Suwa Seikosha Co., Ltd. Patent attorney Mogami Legal procedure correction Letter (spontaneous) Commissioner of the Japan Patent Office -Cat←→Dispute-→←7嬬-Den l Matter e(Display of 1981 Patent Application No. 157032@2 Name of the invention Semiconductor device 3 Amended person Il Kamo Hisashi Nakamura也4 Deputy Director's Attachment Manual Amendment 1 (Voluntary) 1,!# The scope of the main claims is amended as follows.

“Metal gate self-alignment line ff1M08-IC that forms source and drain regions using ion folding method”
Regarding the arrangement of the rectangle that determines the region where the gate oxide film of the transistor is formed, the channel direction of the transistor is defined as iX direction, and Y7jlf perpendicular to this direction.
The position of the rectangular shoulder strap of fl is lighter than the Y-axis center of the gate electrode arrangement of the transistor, and the Y@ of the adjacent metal arrangement.
2. Corrected the drawings 3 and 4 and created the corrected drawing ta.
Attach.

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Claims (1)

Claims: A metal gate cell 7 aligned iljM in which source and drain snow regions are formed using ion implantation. In 5-ro, regarding the rectangular notation that determines one region where the gate oxide film of the transistor is formed, the channel direction of the transistor is set as the X direction. On the sides perpendicular to these, the position of the end line of the rectangle in the Y direction is further away from the Y-axis center line of the gate electrode wiring of the transistor and the position of the Y-axis center of the adjacent metal wiring. A semiconductor device characterized by snow.