JPH0760232B2 - Method of manufacturing thin film transistor matrix - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION SUMMARY The present invention relates to a method of manufacturing a thin film transistor matrix for use in liquid crystal display or the like, a small thin film transistor matrix a parasitic capacitance C _GS,
In order to enable manufacturing without complicating the manufacturing process, the pixel electrode and the drain electrode, which are a source electrode integrated by forming a transparent material film on a transparent insulating substrate, are integrated. And then forming an opaque insulating film made of a non-transparent insulating material self-aligned with the pixel electrode and the drain bus line, and an operating semiconductor layer having a light transmitting property according to a predetermined pattern. And a step of defining the gate insulating film region, and after forming the transparent conductive film,
An image reversal photoresist film is formed on the transparent conductive film, and auxiliary exposure is performed on the image reversal photoresist film from the front side by using a mask having a translucent portion at the intersection of the drain bus line and the gate bus line. Then, baking is performed at a predetermined temperature, then back exposure is performed using the opaque insulating film as a mask, and the pattern edge of the gate electrode is exposed by exposing with light passing through the pixel electrode and the drain bus line. A mask that defines the gate bus line forming portion and a region wider than the region sandwiched by the pattern edges of the gate electrode is used as a light-shielding portion is subjected to auxiliary exposure, and then development processing is performed to form a resist film. And a step of removing the exposed portion of the transparent conductive film using the resist film as a mask.

[Industrial application field]

The present invention relates to a method for manufacturing a thin film transistor matrix used for liquid crystal displays and the like.

[Conventional technology]

In a normal active matrix type liquid crystal display panel using switching elements such as TFT, as shown in FIG. 2, a gate bus line (also referred to as a scan bus line or a scan line) GB for selecting pixels A drain bus line (also referred to as a data bus line or a signal line) DB for supplying display data for each pixel is arranged on the same substrate so as to intersect, and a source electrode S derived from the pixel electrode E is , The drain bus line DB is arranged in parallel and close to the drain bus line DB, and the gate bus line GB intersects with both of them.

In this way, the source electrode S and the drain bus line DB are arranged in parallel and close to each other, and the gate bus line GB is intersected with both, so that the drain electrode D is connected to the drain bus line DB and the gate electrode G is connected to the gate bus line GB. As well as
The space can be effectively used, and the drain bus line DB, the source electrode S, and the pixel electrode E can be formed in the same process, which simplifies the manufacturing process.

[Problems to be solved by the invention]

However, as described above, since the gate bus line and the source electrode overlap with each other in the past, the parasitic capacitance C _{GS is present} between them.
Becomes a source of noise when the liquid crystal panel is driven.

An object of the present invention is to enable a thin film transistor matrix having a small parasitic capacitance C _GS to be manufactured without complicating the manufacturing process.

[Means for solving problems]

In the present invention, the pixel electrode E is also used as the source electrode S, the pixel electrode E and the drain bus line DB are made of a transparent conductive material on the transparent insulating substrate, and an opaque insulating film made of a light-shielding insulating material is formed on the other portions. To form. Next, a laminated body including the operating semiconductor layer and the gate insulating film is formed, and unnecessary portions are selectively removed according to a predetermined pattern to perform element isolation. The pattern used here is such that the element portion and the gate bus line forming portion are integrated.

Next, a transparent conductive film is formed, and the transparent conductive film is patterned by a self-alignment method using the transparent pixel electrode E and the drain bus line DB as a mask to form the gate electrode G. Gate bus line to connect
The intersection of GB or gate bus line GB and drain bus line DB cannot be patterned only by the self-alignment method described above.

Therefore, using an image reversal photoresist film,
First, the crossing portion is exposed and heat-treated to make the exposed portion insoluble in the developing solution, and then the pixel electrode E portion and the drain bus line DB portion are made soluble by the backside exposure method, and the pattern of the gate electrode G is formed. The edges are defined in a self-aligning manner, and finally, a portion other than the pattern including the gate electrode G and the gate pass line GB is exposed to make unnecessary portions soluble, and a developing process is performed to form a resist film.

The transparent conductive film is removed by etching using this resist film as a mask. As described above, the overlap between the gate electrode G and the pixel electrode E, that is, the source electrode S can be extremely reduced, and the parasitic capacitance C _GS can be reduced.

[Action]

The image reversal photoresist is originally a positive type, but when exposed and baked, the exposed portion becomes insoluble in a developing solution as if it were a negative type. But,
The unexposed portion retains a positive type property.

The present invention utilizes this, and the pattern edge of the gate electrode G is defined by the backside exposure method in a self-aligned manner with respect to the pixel electrode E and the drain bus line DB,
By adding a step of making a portion that cannot be defined by the backside exposure method insoluble in a developer by auxiliary exposure plus heat treatment prior to the backside exposure, and a step of making unnecessary portions soluble by auxiliary exposure subsequent to the backside exposure, A desired pattern is formed.

〔Example〕

Hereinafter, as an embodiment of the present invention, an example of manufacturing a thin film transistor matrix will be described with reference to FIGS. Note that (g) to (j) of the same figure show cross sections taken along the line AA of (a), (b), (c), and (f), respectively.

[Refer to (a) and (g) in the same figure]

On a transparent insulating substrate 1 such as a glass substrate, a transparent conductive film (thickness of about 30 to 100 nm) 2 and a contact layer 3 are n ⁺
Laminate an a-Si layer (thickness: about 30 nm). Next, these unnecessary portions are removed to form the pixel electrode E that also serves as the source electrode S and the drain bus line DB, and then a black opaque insulating film 4 such as SiO is formed on the removed trace. The patterning of the opaque insulating film can be performed by a lift-off method using a resist film used as a mask when forming the pixel electrode E and the drain bus line DB.

[Refer to (b) and (h) in the same figure]

Next, the operating semiconductor layer (a-Si layer; thickness of about 30 to 100 nm) 5,
A gate insulating film (SiN film; thickness of about 300 nm) is continuously formed and patterned by an element isolation pattern to form an element region 7. The formation region of the element region 7 includes a region in which the gate electrode G formation region and the gate bus line GB formation region are integrated.

[Refer to (c) and (i) in the same figure]

Next, a transparent conductive film 8 is formed, and an image reversal photoresist (for example, AZ5214 manufactured by Hoechst Co., USA) is formed thereon.
-E) is applied.

[Refer to Figure (d)]

Next, the image reversal photoresist film immediately above the intersection of the drain bus line DB and the gate bus line GB formed in the subsequent step is exposed and then heated to about 120 ° C. As described above, the exposed portion 9 becomes insoluble in the developing solution, and does not change due to the subsequent exposure processing or the like.

Subsequently, back exposure is performed from the back side of the transparent insulating substrate 1. The backside exposure is performed for a time required for the image reversal photoresist film to be sufficiently exposed to light transmitted through the operating semiconductor layer and the like. With this back exposure,
The portion indicated by the satin finish in the figure is exposed and becomes soluble in the developing solution.

[Refer to Figure (e)]

Then, auxiliary exposure is performed using an auxiliary mask having a region surrounded by two lines shown in FIG. 10 as a light shielding part. The light-shielding portion defines the gate bus line GB, and has a pattern larger than the gate electrode G which has already been exposed for defining the pattern edge. This is because the resist outside the pattern edge of the gate electrode G is already soluble and the resist film covering the portion of the gate electrode G remains insoluble.
Since it is not yet developed, when exposed to light, that portion becomes soluble and the pattern collapses. Therefore, the portion of the gate electrode G having insolubility is not exposed as a pattern larger than the gate electrode G.

In this step, the exposed portion is the portion indicated by satin in the figure, and this portion becomes soluble. The area where the matte portion and the matte portion (d) are combined has solubility.

Therefore, by performing development processing after this, a resist film having a pattern surrounded by two lines shown in FIG. 10 is obtained.

[Refer to (f) and (j) in the same figure]

The transparent conductive film 8 is etched by using the resist film as a mask to remove unnecessary portions of the transparent conductive film 8 to form a gate electrode G.

As described above, the staggered type thin film transistor matrix is completed by this embodiment.

In the thus obtained thin film transistor matrix of this example, the gate electrode G is self-aligned with the source electrode S and the drain electrode D, and there is almost no mutual overlap. Therefore, the parasitic capacitance C _GS is greatly reduced compared to the conventional one.

Moreover, although four photomasks are used in this embodiment, two masks 2 are used for the same resist film in the gate electrode G forming step [steps (c) to (e) in the figure]. Therefore, the resist coating work, pre-treatment work, post-treatment work, etc., which accompanies exposure, may be performed only once, and therefore the process is extremely simplified.

〔The invention's effect〕

As described above, according to the present invention, since the parasitic capacitance due to the overlap between the gate electrode and the source electrode (pixel electrode) is reduced, the noise when driving the panel is reduced. Further, the work in the manufacturing process is simple and the manufacturing yield is improved.

[Brief description of drawings]

1 (a) to 1 (j) are explanatory views of an embodiment of the present invention, and FIG. 2 is an explanatory view of conventional problems. In the figure, 1 is a transparent insulating substrate, 2 is a transparent conductive film, 3
Is a contact layer, 4 is a black (opaque) insulating film, 5 is an operating semiconductor layer, 6 is a gate insulating film, 7 is an element region, 8 is a transparent conductive film, 9 is an insoluble region in the exposed portion, and 10 is Auxiliary exposure pattern, D, S, G are drain electrode, source electrode, gate electrode, E is pixel electrode, DB is drain bus line, GB
Indicates a gate bus line.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/786 (72) Inventor Go Kamata 1015 Uedotachu, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Limited (72) Inventor Satoru Kawai 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) Reference JP-A-62-150229 (JP, A)

Claims (1)

[Claims] 1. A pixel electrode (E) in which a transparent material film is selectively formed on a transparent insulating substrate (1) to integrate a source electrode (S) and a drain electrode (D) are integrated. Forming a patterned drain bus line (DB), and then forming an opaque insulating film (4) made of a non-translucent insulating material self-aligned with the pixel electrode (E) and the drain bus line (DB), A step of demarcating a region of the operating semiconductor layer (5) and a gate insulating film (6) having a light-transmitting property according to a predetermined pattern, and forming a transparent conductive film (8), and then performing an image reversal photo on the transparent conductive film. A resist film is formed, and the drain bus line (DB) and the gate bus line (G) are formed on the image reversal photoresist film.
After performing auxiliary exposure from the front side using a mask having a light-transmissive portion at an intersection with B), baking is performed at a predetermined temperature, and back exposure is performed using the opaque insulating film (4) as a mask to obtain the pixel. Electrode (E) and drain bus line (DB)
By exposing with light passing through the gate electrode (G), a pattern edge of the gate electrode (G) is defined, and a region wider than the region sandwiched between the gate bus line (GB) forming portion and the pattern edge of the gate electrode (G) is formed. A step of performing auxiliary exposure using a mask having a light-shielding part, and then performing a development process to form a resist film; and a step of removing the exposed part of the transparent conductive film (8) using the resist film as a mask. A method of manufacturing a thin film transistor matrix, comprising: