GB1581865A - Method of testing a logic system - Google Patents

Method of testing a logic system Download PDF

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Publication number
GB1581865A
GB1581865A GB25726/77A GB2572677A GB1581865A GB 1581865 A GB1581865 A GB 1581865A GB 25726/77 A GB25726/77 A GB 25726/77A GB 2572677 A GB2572677 A GB 2572677A GB 1581865 A GB1581865 A GB 1581865A
Authority
GB
United Kingdom
Prior art keywords
circuit means
array
path
inputs
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB25726/77A
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English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1581865A publication Critical patent/GB1581865A/en
Expired legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G01R31/31858—Delay testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
GB25726/77A 1976-06-30 1977-06-20 Method of testing a logic system Expired GB1581865A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US05/701,054 US4074851A (en) 1976-06-30 1976-06-30 Method of level sensitive testing a functional logic system with embedded array
US05/701,041 US4063080A (en) 1976-06-30 1976-06-30 Method of propagation delay testing a level sensitive array logic system
US05/701,052 US4051352A (en) 1976-06-30 1976-06-30 Level sensitive embedded array logic system

Publications (1)

Publication Number Publication Date
GB1581865A true GB1581865A (en) 1980-12-31

Family

ID=27418716

Family Applications (3)

Application Number Title Priority Date Filing Date
GB25724/77A Expired GB1581863A (en) 1976-06-30 1977-06-20 Testing a logic system
GB25722/77A Expired GB1581861A (en) 1976-06-30 1977-06-20 Integrated semiconductor logic systems
GB25726/77A Expired GB1581865A (en) 1976-06-30 1977-06-20 Method of testing a logic system

Family Applications Before (2)

Application Number Title Priority Date Filing Date
GB25724/77A Expired GB1581863A (en) 1976-06-30 1977-06-20 Testing a logic system
GB25722/77A Expired GB1581861A (en) 1976-06-30 1977-06-20 Integrated semiconductor logic systems

Country Status (6)

Country Link
US (3) US4074851A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (3) JPS533141A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (3) CA1089031A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (3) DE2728318C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2356997A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (3) GB1581863A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054111A1 (en) * 1980-12-17 1982-06-23 International Business Machines Corporation Circuit for use on an LSI chip and for measuring the turn-on and turn-off delays of a logic circuit on said chip
EP0098399A3 (en) * 1982-07-06 1984-08-01 International Business Machines Corporation Test circuitry for determining turn-on and turn-off delays of logic circuits
GB2327127A (en) * 1997-05-27 1999-01-13 Hewlett Packard Co Test chip circuit for on-chip timing characterization

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054111A1 (en) * 1980-12-17 1982-06-23 International Business Machines Corporation Circuit for use on an LSI chip and for measuring the turn-on and turn-off delays of a logic circuit on said chip
US4392105A (en) * 1980-12-17 1983-07-05 International Business Machines Corp. Test circuit for delay measurements on a LSI chip
EP0098399A3 (en) * 1982-07-06 1984-08-01 International Business Machines Corporation Test circuitry for determining turn-on and turn-off delays of logic circuits
GB2327127A (en) * 1997-05-27 1999-01-13 Hewlett Packard Co Test chip circuit for on-chip timing characterization
GB2327127B (en) * 1997-05-27 2002-04-03 Hewlett Packard Co Test chip circuit for on-chip timing characterization

Also Published As

Publication number Publication date
CA1089031A (en) 1980-11-04
US4063080A (en) 1977-12-13
GB1581861A (en) 1980-12-31
JPS5539227B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1980-10-09
DE2728318A1 (de) 1978-01-05
JPS573107B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1982-01-20
US4074851A (en) 1978-02-21
DE2729053C2 (de) 1986-11-06
FR2356997A1 (fr) 1978-01-27
JPS533754A (en) 1978-01-13
FR2356997B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1982-04-23
US4051352A (en) 1977-09-27
DE2728318C2 (de) 1987-04-23
JPS533145A (en) 1978-01-12
CA1075770A (en) 1980-04-15
JPS533141A (en) 1978-01-12
CA1077567A (en) 1980-05-13
DE2728676A1 (de) 1978-01-12
GB1581863A (en) 1980-12-31
DE2728676C2 (de) 1982-04-29
DE2729053A1 (de) 1978-01-12

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