GB1433624A - Multi-level interconnection system - Google Patents

Multi-level interconnection system

Info

Publication number
GB1433624A
GB1433624A GB4432073A GB4432073A GB1433624A GB 1433624 A GB1433624 A GB 1433624A GB 4432073 A GB4432073 A GB 4432073A GB 4432073 A GB4432073 A GB 4432073A GB 1433624 A GB1433624 A GB 1433624A
Authority
GB
United Kingdom
Prior art keywords
layer
etchant
sio
insulating
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4432073A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1433624A publication Critical patent/GB1433624A/en
Expired legal-status Critical Current

Links

Classifications

    • H10W20/42—
    • H10W20/01—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
GB4432073A 1972-10-27 1973-09-21 Multi-level interconnection system Expired GB1433624A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00301570A US3844831A (en) 1972-10-27 1972-10-27 Forming a compact multilevel interconnection metallurgy system for semi-conductor devices

Publications (1)

Publication Number Publication Date
GB1433624A true GB1433624A (en) 1976-04-28

Family

ID=23163957

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4432073A Expired GB1433624A (en) 1972-10-27 1973-09-21 Multi-level interconnection system

Country Status (7)

Country Link
US (1) US3844831A (enExample)
JP (1) JPS5246799B2 (enExample)
CA (1) CA1089112A (enExample)
DE (1) DE2346565C2 (enExample)
FR (1) FR2204891B1 (enExample)
GB (1) GB1433624A (enExample)
IT (1) IT998625B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0182222A3 (en) * 1984-11-09 1987-05-27 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device constructed by polycell technique

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983284A (en) * 1972-06-02 1976-09-28 Thomson-Csf Flat connection for a semiconductor multilayer structure
GB1468346A (en) * 1973-02-28 1977-03-23 Mullard Ltd Devices having conductive tracks at different levels with interconnections therebetween
US4045594A (en) * 1975-12-31 1977-08-30 Ibm Corporation Planar insulation of conductive patterns by chemical vapor deposition and sputtering
US4035276A (en) * 1976-04-29 1977-07-12 Ibm Corporation Making coplanar layers of thin films
US4029562A (en) * 1976-04-29 1977-06-14 Ibm Corporation Forming feedthrough connections for multi-level interconnections metallurgy systems
FR2350697A1 (fr) * 1976-05-06 1977-12-02 Cii Structure perfectionnee de circuits multicouches
DE2642471A1 (de) * 1976-09-21 1978-03-23 Siemens Ag Verfahren zur herstellung von mehrlagenverdrahtungen bei integrierten halbleiterschaltkreisen
DE2936724A1 (de) * 1978-09-11 1980-03-20 Tokyo Shibaura Electric Co Halbleitervorrichtung und verfahren zu ihrer herstellung
JPS5595340A (en) * 1979-01-10 1980-07-19 Chiyou Lsi Gijutsu Kenkyu Kumiai Preparation of semiconductor device
JPS55138868A (en) * 1979-04-17 1980-10-30 Toshiba Corp Bipolar integrated circuit and method of fabricating the same
JPS5643742A (en) * 1979-09-17 1981-04-22 Mitsubishi Electric Corp Manufacture of semiconductor
US4381595A (en) * 1979-10-09 1983-05-03 Mitsubishi Denki Kabushiki Kaisha Process for preparing multilayer interconnection
US4331700A (en) * 1979-11-30 1982-05-25 Rca Corporation Method of making a composite substrate
US4296272A (en) * 1979-11-30 1981-10-20 Rca Corporation Composite substrate
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process
US4452583A (en) * 1981-01-22 1984-06-05 Baker International Corporation Liquid hydrocarbon burning method and apparatus
US4423547A (en) 1981-06-01 1984-01-03 International Business Machines Corporation Method for forming dense multilevel interconnection metallurgy for semiconductor devices
DE3218309A1 (de) * 1982-05-14 1983-11-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von integrierten mos-feldeffekttransistoren mit einer aus metallsiliziden bestehenden zusaetzlichen leiterbahnebene
JPS61170048A (ja) * 1985-01-23 1986-07-31 Nec Corp 半導体装置
US4777852A (en) * 1986-10-02 1988-10-18 Snap-On Tools Corporation Ratcheting screwdriver
JPS63240096A (ja) * 1987-03-27 1988-10-05 富士通株式会社 グリ−ンシ−ト多層法
AU6873791A (en) * 1989-11-16 1991-06-13 Polycon Corporation Hybrid circuit structure and methods of fabrication
US5282922A (en) * 1989-11-16 1994-02-01 Polycon Corporation Hybrid circuit structures and methods of fabrication
US5096124A (en) * 1990-10-05 1992-03-17 Halliburton Company Burner apparatus
US5453401A (en) * 1991-05-01 1995-09-26 Motorola, Inc. Method for reducing corrosion of a metal surface containing at least aluminum and copper
US5234769A (en) * 1992-04-16 1993-08-10 Deposition Sciences, Inc. Wear resistant transparent dielectric coatings
US5612254A (en) * 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
US5416278A (en) 1993-03-01 1995-05-16 Motorola, Inc. Feedthrough via connection
US5413962A (en) * 1994-07-15 1995-05-09 United Microelectronics Corporation Multi-level conductor process in VLSI fabrication utilizing an air bridge
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5736457A (en) * 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization
TW408420B (en) * 1998-08-14 2000-10-11 Mosel Vitelic Inc A method to measure if the connecting via in the metal wiring layer is aligned correctly
CN117324381A (zh) * 2023-11-02 2024-01-02 北京工业大学 一种异温轧制制备铝/铝/钽三层复合材料的方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3290565A (en) * 1963-10-24 1966-12-06 Philco Corp Glass enclosed, passivated semiconductor with contact means of alternate layers of chromium, silver and chromium
US3266127A (en) * 1964-01-27 1966-08-16 Ibm Method of forming contacts on semiconductors
US3406043A (en) * 1964-11-09 1968-10-15 Western Electric Co Integrated circuit containing multilayer tantalum compounds
FR1496985A (fr) * 1965-10-19 1967-10-06 Sylvania Electric Prod Procédé de fabrication de semi-conducteurs munis de conducteurs de connexion et semi-conducteurs ainsi obtenus
US3597667A (en) * 1966-03-01 1971-08-03 Gen Electric Silicon oxide-silicon nitride coatings for semiconductor devices
US3641661A (en) * 1968-06-25 1972-02-15 Texas Instruments Inc Method of fabricating integrated circuit arrays
US3634929A (en) * 1968-11-02 1972-01-18 Tokyo Shibaura Electric Co Method of manufacturing semiconductor integrated circuits
GB1286737A (en) * 1969-10-15 1972-08-23 Itt Multilevel conductive systems
US3700508A (en) * 1970-06-25 1972-10-24 Gen Instrument Corp Fabrication of integrated microcircuit devices
US3760242A (en) * 1972-03-06 1973-09-18 Ibm Coated semiconductor structures and methods of forming protective coverings on such structures

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0182222A3 (en) * 1984-11-09 1987-05-27 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device constructed by polycell technique
US4716452A (en) * 1984-11-09 1987-12-29 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device constructed by polycell technique

Also Published As

Publication number Publication date
FR2204891A1 (enExample) 1974-05-24
DE2346565C2 (de) 1983-11-10
IT998625B (it) 1976-02-20
CA1089112A (en) 1980-11-04
US3844831A (en) 1974-10-29
JPS4975290A (enExample) 1974-07-19
FR2204891B1 (enExample) 1977-08-05
JPS5246799B2 (enExample) 1977-11-28
DE2346565A1 (de) 1974-05-02

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19920921