FR3123759B1 - Procede de fabrication d’une structure semi-conductrice comprenant une couche utile en carbure de silicium aux proprietes electriques ameliorees - Google Patents
Procede de fabrication d’une structure semi-conductrice comprenant une couche utile en carbure de silicium aux proprietes electriques ameliorees Download PDFInfo
- Publication number
- FR3123759B1 FR3123759B1 FR2105848A FR2105848A FR3123759B1 FR 3123759 B1 FR3123759 B1 FR 3123759B1 FR 2105848 A FR2105848 A FR 2105848A FR 2105848 A FR2105848 A FR 2105848A FR 3123759 B1 FR3123759 B1 FR 3123759B1
- Authority
- FR
- France
- Prior art keywords
- donor substrate
- silicon carbide
- semiconductor structure
- front surface
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P10/00—Bonding of wafers, substrates or parts of devices
- H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P10/00—Bonding of wafers, substrates or parts of devices
- H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
- H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/60—Wet etching
- H10P50/64—Wet etching of semiconductor materials
- H10P50/642—Chemical etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2105848A FR3123759B1 (fr) | 2021-06-03 | 2021-06-03 | Procede de fabrication d’une structure semi-conductrice comprenant une couche utile en carbure de silicium aux proprietes electriques ameliorees |
| US18/566,474 US20240312831A1 (en) | 2021-06-03 | 2022-05-25 | Method for producing a semiconductor structure comprising a useful layer made of silicon carbide, with improved electrical properties |
| JP2023574538A JP2024521573A (ja) | 2021-06-03 | 2022-05-25 | 改善された電気特性を有する、炭化ケイ素から作製された動作層を備える半導体構造体を製造するための方法 |
| IL309011A IL309011A (en) | 2021-06-03 | 2022-05-25 | Method for producing a semiconductor structure comprising a useful layer made of silicon carbide, with improved electrical properties |
| PCT/FR2022/051000 WO2022254131A1 (fr) | 2021-06-03 | 2022-05-25 | Procede de fabrication d'une structure semi-conductrice comprenant une couche utile en carbure de silicium aux proprietes electriques ameliorees |
| CN202280039520.6A CN118302839A (zh) | 2021-06-03 | 2022-05-25 | 制造包括具有改进的电性能的由碳化硅制成的工作层的半导体结构体的方法 |
| KR1020237040244A KR20240067221A (ko) | 2021-06-03 | 2022-05-25 | 개선된 전기적 속성들을 갖는 탄화규소로 만들어진 작업 층을 포함하는 반도체 구조체의 제조 프로세스 |
| EP22731276.6A EP4348701B1 (fr) | 2021-06-03 | 2022-05-25 | Procede de fabrication d'une structure semi-conductrice comprenant une couche utile en carbure de silicium aux proprietes electriques ameliorees |
| TW111119672A TW202303968A (zh) | 2021-06-03 | 2022-05-26 | 用於製作包含具改善電氣特性之碳化矽製工作層之半導體結構之方法 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2105848A FR3123759B1 (fr) | 2021-06-03 | 2021-06-03 | Procede de fabrication d’une structure semi-conductrice comprenant une couche utile en carbure de silicium aux proprietes electriques ameliorees |
| FR2105848 | 2021-06-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR3123759A1 FR3123759A1 (fr) | 2022-12-09 |
| FR3123759B1 true FR3123759B1 (fr) | 2023-06-23 |
Family
ID=77519224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR2105848A Active FR3123759B1 (fr) | 2021-06-03 | 2021-06-03 | Procede de fabrication d’une structure semi-conductrice comprenant une couche utile en carbure de silicium aux proprietes electriques ameliorees |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US20240312831A1 (https=) |
| EP (1) | EP4348701B1 (https=) |
| JP (1) | JP2024521573A (https=) |
| KR (1) | KR20240067221A (https=) |
| CN (1) | CN118302839A (https=) |
| FR (1) | FR3123759B1 (https=) |
| IL (1) | IL309011A (https=) |
| TW (1) | TW202303968A (https=) |
| WO (1) | WO2022254131A1 (https=) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6387375B2 (ja) * | 2016-07-19 | 2018-09-05 | 株式会社サイコックス | 半導体基板 |
| EP3584821B1 (en) * | 2017-02-16 | 2025-03-12 | Shin-Etsu Chemical Co., Ltd. | Compound semiconductor laminate substrate, method for manufacturing same, and semiconductor element |
-
2021
- 2021-06-03 FR FR2105848A patent/FR3123759B1/fr active Active
-
2022
- 2022-05-25 US US18/566,474 patent/US20240312831A1/en active Pending
- 2022-05-25 CN CN202280039520.6A patent/CN118302839A/zh active Pending
- 2022-05-25 JP JP2023574538A patent/JP2024521573A/ja active Pending
- 2022-05-25 KR KR1020237040244A patent/KR20240067221A/ko active Pending
- 2022-05-25 IL IL309011A patent/IL309011A/en unknown
- 2022-05-25 EP EP22731276.6A patent/EP4348701B1/fr active Active
- 2022-05-25 WO PCT/FR2022/051000 patent/WO2022254131A1/fr not_active Ceased
- 2022-05-26 TW TW111119672A patent/TW202303968A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| US20240312831A1 (en) | 2024-09-19 |
| WO2022254131A1 (fr) | 2022-12-08 |
| TW202303968A (zh) | 2023-01-16 |
| CN118302839A (zh) | 2024-07-05 |
| FR3123759A1 (fr) | 2022-12-09 |
| KR20240067221A (ko) | 2024-05-16 |
| EP4348701B1 (fr) | 2025-06-25 |
| JP2024521573A (ja) | 2024-06-03 |
| EP4348701C0 (fr) | 2025-06-25 |
| IL309011A (en) | 2024-01-01 |
| EP4348701A1 (fr) | 2024-04-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PLFP | Fee payment |
Year of fee payment: 2 |
|
| PLSC | Publication of the preliminary search report |
Effective date: 20221209 |
|
| PLFP | Fee payment |
Year of fee payment: 3 |
|
| PLFP | Fee payment |
Year of fee payment: 4 |
|
| PLFP | Fee payment |
Year of fee payment: 5 |