TW202303968A - 用於製作包含具改善電氣特性之碳化矽製工作層之半導體結構之方法 - Google Patents

用於製作包含具改善電氣特性之碳化矽製工作層之半導體結構之方法 Download PDF

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Publication number
TW202303968A
TW202303968A TW111119672A TW111119672A TW202303968A TW 202303968 A TW202303968 A TW 202303968A TW 111119672 A TW111119672 A TW 111119672A TW 111119672 A TW111119672 A TW 111119672A TW 202303968 A TW202303968 A TW 202303968A
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TW
Taiwan
Prior art keywords
donor substrate
semiconductor structure
layer
working layer
front side
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TW111119672A
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English (en)
Chinese (zh)
Inventor
艾利克斯 德朗
葛威塔茲 高爾丁
瑟弗林 盧西耶
華特 史渥森班曲
茱莉 衛迪茲
伊曼紐爾 羅蘭
Original Assignee
法商索泰克公司
法國原子能與替代能源委員會
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Application filed by 法商索泰克公司, 法國原子能與替代能源委員會 filed Critical 法商索泰克公司
Publication of TW202303968A publication Critical patent/TW202303968A/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
TW111119672A 2021-06-03 2022-05-26 用於製作包含具改善電氣特性之碳化矽製工作層之半導體結構之方法 TW202303968A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FRFR2105848 2021-06-03
FR2105848A FR3123759B1 (fr) 2021-06-03 2021-06-03 Procede de fabrication d’une structure semi-conductrice comprenant une couche utile en carbure de silicium aux proprietes electriques ameliorees

Publications (1)

Publication Number Publication Date
TW202303968A true TW202303968A (zh) 2023-01-16

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW111119672A TW202303968A (zh) 2021-06-03 2022-05-26 用於製作包含具改善電氣特性之碳化矽製工作層之半導體結構之方法

Country Status (9)

Country Link
US (1) US20240312831A1 (https=)
EP (1) EP4348701B1 (https=)
JP (1) JP2024521573A (https=)
KR (1) KR20240067221A (https=)
CN (1) CN118302839A (https=)
FR (1) FR3123759B1 (https=)
IL (1) IL309011A (https=)
TW (1) TW202303968A (https=)
WO (1) WO2022254131A1 (https=)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6387375B2 (ja) * 2016-07-19 2018-09-05 株式会社サイコックス 半導体基板
EP3584821B1 (en) * 2017-02-16 2025-03-12 Shin-Etsu Chemical Co., Ltd. Compound semiconductor laminate substrate, method for manufacturing same, and semiconductor element

Also Published As

Publication number Publication date
US20240312831A1 (en) 2024-09-19
WO2022254131A1 (fr) 2022-12-08
CN118302839A (zh) 2024-07-05
FR3123759A1 (fr) 2022-12-09
KR20240067221A (ko) 2024-05-16
EP4348701B1 (fr) 2025-06-25
JP2024521573A (ja) 2024-06-03
EP4348701C0 (fr) 2025-06-25
IL309011A (en) 2024-01-01
FR3123759B1 (fr) 2023-06-23
EP4348701A1 (fr) 2024-04-10

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