KR20240067221A - 개선된 전기적 속성들을 갖는 탄화규소로 만들어진 작업 층을 포함하는 반도체 구조체의 제조 프로세스 - Google Patents

개선된 전기적 속성들을 갖는 탄화규소로 만들어진 작업 층을 포함하는 반도체 구조체의 제조 프로세스 Download PDF

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Publication number
KR20240067221A
KR20240067221A KR1020237040244A KR20237040244A KR20240067221A KR 20240067221 A KR20240067221 A KR 20240067221A KR 1020237040244 A KR1020237040244 A KR 1020237040244A KR 20237040244 A KR20237040244 A KR 20237040244A KR 20240067221 A KR20240067221 A KR 20240067221A
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South Korea
Prior art keywords
donor substrate
layer
semiconductor structure
manufacturing process
working layer
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KR1020237040244A
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English (en)
Korean (ko)
Inventor
알렉시스 드루인
지웰타츠 고댕
세베린 로우치어
왈터 슈와젠바흐
줄리에 위디즈
엠마누엘 롤란드
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소이텍
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Publication of KR20240067221A publication Critical patent/KR20240067221A/ko
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Classifications

    • H01L21/185—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H01L21/304—
    • H01L21/30604—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
KR1020237040244A 2021-06-03 2022-05-25 개선된 전기적 속성들을 갖는 탄화규소로 만들어진 작업 층을 포함하는 반도체 구조체의 제조 프로세스 Pending KR20240067221A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FRFR2105848 2021-06-03
FR2105848A FR3123759B1 (fr) 2021-06-03 2021-06-03 Procede de fabrication d’une structure semi-conductrice comprenant une couche utile en carbure de silicium aux proprietes electriques ameliorees
PCT/FR2022/051000 WO2022254131A1 (fr) 2021-06-03 2022-05-25 Procede de fabrication d'une structure semi-conductrice comprenant une couche utile en carbure de silicium aux proprietes electriques ameliorees

Publications (1)

Publication Number Publication Date
KR20240067221A true KR20240067221A (ko) 2024-05-16

Family

ID=77519224

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020237040244A Pending KR20240067221A (ko) 2021-06-03 2022-05-25 개선된 전기적 속성들을 갖는 탄화규소로 만들어진 작업 층을 포함하는 반도체 구조체의 제조 프로세스

Country Status (9)

Country Link
US (1) US20240312831A1 (https=)
EP (1) EP4348701B1 (https=)
JP (1) JP2024521573A (https=)
KR (1) KR20240067221A (https=)
CN (1) CN118302839A (https=)
FR (1) FR3123759B1 (https=)
IL (1) IL309011A (https=)
TW (1) TW202303968A (https=)
WO (1) WO2022254131A1 (https=)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6387375B2 (ja) * 2016-07-19 2018-09-05 株式会社サイコックス 半導体基板
EP3584821B1 (en) * 2017-02-16 2025-03-12 Shin-Etsu Chemical Co., Ltd. Compound semiconductor laminate substrate, method for manufacturing same, and semiconductor element

Also Published As

Publication number Publication date
US20240312831A1 (en) 2024-09-19
WO2022254131A1 (fr) 2022-12-08
TW202303968A (zh) 2023-01-16
CN118302839A (zh) 2024-07-05
FR3123759A1 (fr) 2022-12-09
EP4348701B1 (fr) 2025-06-25
JP2024521573A (ja) 2024-06-03
EP4348701C0 (fr) 2025-06-25
IL309011A (en) 2024-01-01
FR3123759B1 (fr) 2023-06-23
EP4348701A1 (fr) 2024-04-10

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