FR3117303B1 - Réduction des zones de contraintes dans les joints brasés d’une carte électronique - Google Patents

Réduction des zones de contraintes dans les joints brasés d’une carte électronique Download PDF

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Publication number
FR3117303B1
FR3117303B1 FR2012909A FR2012909A FR3117303B1 FR 3117303 B1 FR3117303 B1 FR 3117303B1 FR 2012909 A FR2012909 A FR 2012909A FR 2012909 A FR2012909 A FR 2012909A FR 3117303 B1 FR3117303 B1 FR 3117303B1
Authority
FR
France
Prior art keywords
reduction
electronic board
soldered joints
stress zones
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2012909A
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English (en)
Other versions
FR3117303A1 (fr
Inventor
Philippe Chocteau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Safran Electronics and Defense SAS
Original Assignee
Safran Electronics and Defense SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Safran Electronics and Defense SAS filed Critical Safran Electronics and Defense SAS
Priority to FR2012909A priority Critical patent/FR3117303B1/fr
Publication of FR3117303A1 publication Critical patent/FR3117303A1/fr
Application granted granted Critical
Publication of FR3117303B1 publication Critical patent/FR3117303B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

La présente invention concerne une carte électronique (1) comprenant : un circuit imprimé (2) comprenant une couche électriquement isolante (9) présentant une face de connexion (3) sur laquelle est fixée une couche conductrice traitée de sorte à former deux plages (4) ; un composant électronique (5) comprenant deux terminaisons (6), chaque terminaison (6) étant fixée sur une plage de brasage correspondante ; et une rainure (8) formée dans la couche électriquement isolante (9) à proximité d’au moins une des plages (4), ladite rainure (8) présentant un fond et étant ouverte au niveau de la face de connexion (3). Figure pour l’abrégé : Fig. 1
FR2012909A 2020-12-09 2020-12-09 Réduction des zones de contraintes dans les joints brasés d’une carte électronique Active FR3117303B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR2012909A FR3117303B1 (fr) 2020-12-09 2020-12-09 Réduction des zones de contraintes dans les joints brasés d’une carte électronique

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2012909 2020-12-09
FR2012909A FR3117303B1 (fr) 2020-12-09 2020-12-09 Réduction des zones de contraintes dans les joints brasés d’une carte électronique

Publications (2)

Publication Number Publication Date
FR3117303A1 FR3117303A1 (fr) 2022-06-10
FR3117303B1 true FR3117303B1 (fr) 2023-01-06

Family

ID=74871536

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2012909A Active FR3117303B1 (fr) 2020-12-09 2020-12-09 Réduction des zones de contraintes dans les joints brasés d’une carte électronique

Country Status (1)

Country Link
FR (1) FR3117303B1 (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2674586B2 (ja) * 1995-10-25 1997-11-12 日本電気株式会社 プリント配線基板の実装構造
JP4108784B2 (ja) * 1997-05-19 2008-06-25 松下電器産業株式会社 回路基板
JP2003110238A (ja) * 2001-09-28 2003-04-11 Murata Mfg Co Ltd ガラスセラミック多層基板の製造方法
JP2004363379A (ja) * 2003-06-05 2004-12-24 Sanyo Electric Co Ltd 半導体装置
FR3069128B1 (fr) 2017-07-13 2020-06-26 Safran Electronics & Defense Fixation d'un cms sur une couche isolante avec un joint de brasure dans une cavite realisee dans une couche isolante
FR3075558B1 (fr) 2017-12-19 2019-11-15 Safran Electronics & Defense Suppression des zones de forte contrainte dans les assemblages electroniques

Also Published As

Publication number Publication date
FR3117303A1 (fr) 2022-06-10

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