FR2874745A1 - Plaque semiconductrice presentant une structure stratifiee avec de faibles warp et bow, et procedes pour sa preparation - Google Patents

Plaque semiconductrice presentant une structure stratifiee avec de faibles warp et bow, et procedes pour sa preparation

Info

Publication number
FR2874745A1
FR2874745A1 FR0508769A FR0508769A FR2874745A1 FR 2874745 A1 FR2874745 A1 FR 2874745A1 FR 0508769 A FR0508769 A FR 0508769A FR 0508769 A FR0508769 A FR 0508769A FR 2874745 A1 FR2874745 A1 FR 2874745A1
Authority
FR
France
Prior art keywords
bow
methods
same
less
preparing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR0508769A
Other languages
English (en)
Other versions
FR2874745B1 (fr
Inventor
Markus Blietz
Robert Holzl
Reinhold Wahlich
Andreas Huber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siltronic AG
Original Assignee
Siltronic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic AG filed Critical Siltronic AG
Publication of FR2874745A1 publication Critical patent/FR2874745A1/fr
Application granted granted Critical
Publication of FR2874745B1 publication Critical patent/FR2874745B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Laminated Bodies (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne une plaque semi-conductrice, et des procédés de fabrication de celle-ci, comprenant une tranche substrat en silicium et une couche isolante électrique portant une couche semiconductrice, préparée selon un procédé de transfert de couche comprenant au moins une étape RTA, la tranche substrat présente une densité de BMD dans le domaine allant de 1.103/cm2 à 1.106/cm2 et présentant ainsi un Warp inférieur à 30 m, un DeltaWarp inférieur à 30 m, un Bow inférieur à 10 m et un DeltaBow inférieur à 10 m.
FR0508769A 2004-08-26 2005-08-26 Plaque semiconductrice presentant une structure stratifiee avec de faibles warp et bow, et procedes pour sa preparation Active FR2874745B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102004041378A DE102004041378B4 (de) 2004-08-26 2004-08-26 Halbleiterscheibe mit Schichtstruktur mit geringem Warp und Bow sowie Verfahren zu ihrer Herstellung

Publications (2)

Publication Number Publication Date
FR2874745A1 true FR2874745A1 (fr) 2006-03-03
FR2874745B1 FR2874745B1 (fr) 2009-11-27

Family

ID=35745567

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0508769A Active FR2874745B1 (fr) 2004-08-26 2005-08-26 Plaque semiconductrice presentant une structure stratifiee avec de faibles warp et bow, et procedes pour sa preparation

Country Status (7)

Country Link
US (2) US20060046431A1 (fr)
JP (1) JP2006066913A (fr)
KR (1) KR100750978B1 (fr)
CN (1) CN100407429C (fr)
DE (1) DE102004041378B4 (fr)
FR (1) FR2874745B1 (fr)
TW (1) TWI303077B (fr)

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JP5119677B2 (ja) * 2007-02-16 2013-01-16 株式会社Ｓｕｍｃｏ シリコンウェーハ及びその製造方法
FR2914495B1 (fr) * 2007-03-29 2009-10-02 Soitec Silicon On Insulator Amelioration de la qualite d'une couche mince par recuit thermique haute temperature.
US7928534B2 (en) * 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US8736050B2 (en) 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US8759949B2 (en) * 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
US8158489B2 (en) * 2009-06-26 2012-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of TSV backside interconnects by modifying carrier wafers
US8174124B2 (en) 2010-04-08 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy pattern in wafer backside routing
DE102010027766B4 (de) 2010-04-15 2017-02-09 Daniela Claudia Szasz Kühlanordnung für elektrische Komponenten eines elektrischen Gerätes
US9945048B2 (en) * 2012-06-15 2018-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method
US10141413B2 (en) 2013-03-13 2018-11-27 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer strength by control of uniformity of edge bulk micro defects
US9064823B2 (en) * 2013-03-13 2015-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method for qualifying a semiconductor wafer for subsequent processing
WO2016081367A1 (fr) 2014-11-18 2016-05-26 Sunedison Semiconductor Limited Substrat de silicium sur isolant de grande résistivité comprenant une couche de piégeage de charge formée par co-implantation he-n2
EP3221885B1 (fr) 2014-11-18 2019-10-23 GlobalWafers Co., Ltd. Plaquette semi-conducteur sur isolant haute résistivité et procédé de fabrication
CN107533953B (zh) * 2015-03-03 2021-05-11 环球晶圆股份有限公司 具有可控膜应力的在硅衬底上沉积电荷捕获多晶硅膜的方法
CN114496732B (zh) 2015-06-01 2023-03-03 环球晶圆股份有限公司 制造绝缘体上硅锗的方法
FR3037438B1 (fr) * 2015-06-09 2017-06-16 Soitec Silicon On Insulator Procede de fabrication d'un element semi-conducteur comprenant une couche de piegeage de charges
SG10201913407TA (en) 2015-11-20 2020-03-30 Globalwafers Co Ltd Manufacturing method of smoothing a semiconductor surface
DE102015224983B4 (de) * 2015-12-11 2019-01-24 Siltronic Ag Halbleiterscheibe aus einkristallinem Silizium und Verfahren zu deren Herstellung
US11142844B2 (en) 2016-06-08 2021-10-12 Globalwafers Co., Ltd. High resistivity single crystal silicon ingot and wafer having improved mechanical strength
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
FR3058561B1 (fr) * 2016-11-04 2018-11-02 Soitec Procede de fabrication d'un element semi-conducteur comprenant un substrat hautement resistif
US10818540B2 (en) 2018-06-08 2020-10-27 Globalwafers Co., Ltd. Method for transfer of a thin layer of silicon
CN114156179A (zh) * 2021-10-29 2022-03-08 中国科学院上海微系统与信息技术研究所 一种改善绝缘层上硅晶圆表面粗糙度的方法

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Also Published As

Publication number Publication date
US7820549B2 (en) 2010-10-26
KR20060050693A (ko) 2006-05-19
TW200608458A (en) 2006-03-01
DE102004041378A1 (de) 2006-03-02
DE102004041378B4 (de) 2010-07-08
JP2006066913A (ja) 2006-03-09
TWI303077B (en) 2008-11-11
US20060046431A1 (en) 2006-03-02
CN100407429C (zh) 2008-07-30
US20080122043A1 (en) 2008-05-29
FR2874745B1 (fr) 2009-11-27
CN1741276A (zh) 2006-03-01
KR100750978B1 (ko) 2007-08-22

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