FR2712439B1 - Circuit et procédé de génération d'un signal de sortie retardé. - Google Patents

Circuit et procédé de génération d'un signal de sortie retardé.

Info

Publication number
FR2712439B1
FR2712439B1 FR9413273A FR9413273A FR2712439B1 FR 2712439 B1 FR2712439 B1 FR 2712439B1 FR 9413273 A FR9413273 A FR 9413273A FR 9413273 A FR9413273 A FR 9413273A FR 2712439 B1 FR2712439 B1 FR 2712439B1
Authority
FR
France
Prior art keywords
generating
circuit
output signal
delayed output
delayed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9413273A
Other languages
English (en)
Other versions
FR2712439A1 (fr
Inventor
Jeannie Han Kosiec
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of FR2712439A1 publication Critical patent/FR2712439A1/fr
Application granted granted Critical
Publication of FR2712439B1 publication Critical patent/FR2712439B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)
FR9413273A 1993-11-09 1994-11-07 Circuit et procédé de génération d'un signal de sortie retardé. Expired - Fee Related FR2712439B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15065393A 1993-11-09 1993-11-09

Publications (2)

Publication Number Publication Date
FR2712439A1 FR2712439A1 (fr) 1995-05-19
FR2712439B1 true FR2712439B1 (fr) 1996-02-23

Family

ID=22535453

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9413273A Expired - Fee Related FR2712439B1 (fr) 1993-11-09 1994-11-07 Circuit et procédé de génération d'un signal de sortie retardé.

Country Status (7)

Country Link
US (1) US5801567A (fr)
AU (1) AU7981094A (fr)
FR (1) FR2712439B1 (fr)
GB (1) GB2289178B (fr)
MX (1) MXPA94008676A (fr)
WO (1) WO1995013656A1 (fr)
ZA (1) ZA948524B (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3714762B2 (ja) * 1997-03-19 2005-11-09 富士通株式会社 遅延回路および半導体記憶装置
US6097231A (en) * 1998-05-29 2000-08-01 Ramtron International Corporation CMOS RC equivalent delay circuit
US6307417B1 (en) 1999-08-24 2001-10-23 Robert J. Proebsting Integrated circuit output buffers having reduced power consumption requirements and methods of operating same
JP3586612B2 (ja) * 2000-03-08 2004-11-10 エルピーダメモリ株式会社 遅延回路
US6549042B2 (en) 2000-06-23 2003-04-15 Integrated Device Technology, Inc. Complementary data line driver circuits with conditional charge recycling capability that may be used in random access and content addressable memory devices and method of operating same
KR100521360B1 (ko) * 2002-04-12 2005-10-12 삼성전자주식회사 전원 전압에 가변되지 않는 지연 회로 및 이를 포함하는반도체 메모리 장치
US6958646B1 (en) * 2002-05-28 2005-10-25 Impinj, Inc. Autozeroing floating-gate amplifier
US7268605B2 (en) * 2004-06-14 2007-09-11 Rambus, Inc. Technique for operating a delay circuit
US8710805B2 (en) * 2011-09-19 2014-04-29 Westinghouse Electric Company, Llc Squib control circuit
US8680901B2 (en) * 2012-08-06 2014-03-25 Texas Instruments Incorporated Power on reset generation circuits in integrated circuits
KR102290384B1 (ko) 2015-02-16 2021-08-17 삼성전자주식회사 누설 전류 기반의 지연 회로

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3331967A (en) * 1963-05-31 1967-07-18 American Mach & Foundry Time delay circuit employing scr controlled by timing-capacitor having plural current paths for total discharging thereof
JPS52119160A (en) * 1976-03-31 1977-10-06 Nec Corp Semiconductor circuit with insulating gate type field dffect transisto r
US4322643A (en) * 1980-04-28 1982-03-30 Rca Corporation Digital phase comparator with improved sensitivity for small phase differences
US4378509A (en) * 1980-07-10 1983-03-29 Motorola, Inc. Linearized digital phase and frequency detector
JPS59123320A (ja) * 1982-12-29 1984-07-17 Fujitsu Ltd タイマ回路
JPS60223321A (ja) * 1984-04-20 1985-11-07 Toshiba Corp タイマ回路
US4707626A (en) * 1984-07-26 1987-11-17 Texas Instruments Incorporated Internal time-out circuit for CMOS dynamic RAM
JPS6153759A (ja) * 1984-08-23 1986-03-17 Fujitsu Ltd 発振回路
KR970000560B1 (ko) * 1986-10-01 1997-01-13 아오이 죠이치 반도체집적회로
JPS63142714A (ja) * 1986-12-04 1988-06-15 Nec Corp デイジタル集積回路
JPH01137817A (ja) * 1987-11-25 1989-05-30 Toshiba Corp 遅延回路
US4959816A (en) * 1987-12-28 1990-09-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US5182479A (en) * 1988-06-24 1993-01-26 U.S. Philips Corp. Gate circuit having increased voltage handling capability
JPH0322611A (ja) * 1989-06-19 1991-01-31 Nec Corp パルス発生回路
US5130582A (en) * 1989-09-19 1992-07-14 Tdk Corporation Delay circuit which is free from temperature variation, power supply voltage variation and process variation
KR920022699A (ko) * 1991-05-16 1992-12-19 김광호 지연 보상 회로
US5175452A (en) * 1991-09-30 1992-12-29 Data Delay Devices, Inc. Programmable compensated digital delay circuit
US5216289A (en) * 1991-10-24 1993-06-01 Intel Corporation Asynchronous reset scheme for ultra-low noise port tri-state output driver circuit

Also Published As

Publication number Publication date
MXPA94008676A (es) 2005-06-20
GB9513635D0 (en) 1995-09-06
GB2289178B (en) 1998-05-20
GB2289178A (en) 1995-11-08
US5801567A (en) 1998-09-01
FR2712439A1 (fr) 1995-05-19
ZA948524B (en) 1995-06-23
AU7981094A (en) 1995-05-29
WO1995013656A1 (fr) 1995-05-18

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090731