FR2683934A1 - Circuit pour augmenter la vitesse de fonctionnement d'un dispositif de memoire a semi-conducteur. - Google Patents

Circuit pour augmenter la vitesse de fonctionnement d'un dispositif de memoire a semi-conducteur. Download PDF

Info

Publication number
FR2683934A1
FR2683934A1 FR9211195A FR9211195A FR2683934A1 FR 2683934 A1 FR2683934 A1 FR 2683934A1 FR 9211195 A FR9211195 A FR 9211195A FR 9211195 A FR9211195 A FR 9211195A FR 2683934 A1 FR2683934 A1 FR 2683934A1
Authority
FR
France
Prior art keywords
signal
detection
input
spg
equalization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR9211195A
Other languages
English (en)
French (fr)
Inventor
Lee Hyong-Gon
Jang Cheol-Ung
Cho Sung-Hee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2683934A1 publication Critical patent/FR2683934A1/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
FR9211195A 1991-11-19 1992-09-21 Circuit pour augmenter la vitesse de fonctionnement d'un dispositif de memoire a semi-conducteur. Pending FR2683934A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910020595A KR930010990A (ko) 1991-11-19 1991-11-19 반도체 메모리 장치에서의 스피드 향상을 위한 회로

Publications (1)

Publication Number Publication Date
FR2683934A1 true FR2683934A1 (fr) 1993-05-21

Family

ID=19323071

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9211195A Pending FR2683934A1 (fr) 1991-11-19 1992-09-21 Circuit pour augmenter la vitesse de fonctionnement d'un dispositif de memoire a semi-conducteur.

Country Status (8)

Country Link
JP (1) JPH05217378A (enrdf_load_stackoverflow)
KR (1) KR930010990A (enrdf_load_stackoverflow)
CN (1) CN1072528A (enrdf_load_stackoverflow)
DE (1) DE4234153A1 (enrdf_load_stackoverflow)
FR (1) FR2683934A1 (enrdf_load_stackoverflow)
GB (1) GB2261754A (enrdf_load_stackoverflow)
IT (1) IT1258253B (enrdf_load_stackoverflow)
TW (1) TW198157B (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940002860A (ko) * 1992-07-27 1994-02-19 김광호 어드레스 변동 검출기
US8688955B2 (en) 2010-08-13 2014-04-01 Micron Technology, Inc. Line termination methods and apparatus
CN102723100A (zh) * 2012-05-23 2012-10-10 常州芯奇微电子科技有限公司 多功能内存接口电路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0278155A2 (en) * 1987-02-10 1988-08-17 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory
US4962324A (en) * 1988-04-30 1990-10-09 Samsung Electronics, Ltd. Equalizing circuit for a sense amplifier
EP0419852A2 (en) * 1989-09-22 1991-04-03 Texas Instruments Incorporated A memory with selective address transition detection for cache operation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6224875A (ja) * 1985-07-24 1987-02-02 Sekisui Chem Co Ltd 溶接装置
JPH0640439B2 (ja) * 1986-02-17 1994-05-25 日本電気株式会社 半導体記憶装置
JPH0814989B2 (ja) * 1989-05-09 1996-02-14 日本電気株式会社 内部同期型スタティックｒａｍ
US4969125A (en) * 1989-06-23 1990-11-06 International Business Machines Corporation Asynchronous segmented precharge architecture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0278155A2 (en) * 1987-02-10 1988-08-17 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory
US4962324A (en) * 1988-04-30 1990-10-09 Samsung Electronics, Ltd. Equalizing circuit for a sense amplifier
EP0419852A2 (en) * 1989-09-22 1991-04-03 Texas Instruments Incorporated A memory with selective address transition detection for cache operation

Also Published As

Publication number Publication date
IT1258253B (it) 1996-02-22
ITMI922575A0 (it) 1992-11-10
CN1072528A (zh) 1993-05-26
GB2261754A (en) 1993-05-26
KR930010990A (ko) 1993-06-23
ITMI922575A1 (it) 1994-05-10
TW198157B (enrdf_load_stackoverflow) 1993-01-11
GB9224303D0 (en) 1993-01-06
JPH05217378A (ja) 1993-08-27
DE4234153A1 (de) 1993-05-27

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