FR2683934A1 - CIRCUIT FOR INCREASING THE OPERATING SPEED OF A SEMICONDUCTOR MEMORY DEVICE. - Google Patents

Abstract

Semiconductor memory device with an address transition detection circuit including an input signal detector (100B) receiving an externally input signal (APi, APiB) which is buffered to detect a desired signal, control means (100C) for producing a signal for controlling a sense amplifier in response to the output signal of said input signal detector (100B); and an equalization signal generator (100D) receiving the output signals (SPG, SACS) from the input signal detector (100B) and the control means (100C), to produce an equalization signal (PHIpzd) for equalizing a pair of bit lines and/or data input/output lines, whereby said pair of bit lines and/or pair of data input/output lines are always equalized while said amplifier detection is not implemented.

Description

CIRCUIT FOR INCREASING OPERATING SPEED

  OF A SEMICONDUCTOR MEMORY DEVICE

  The present invention relates to a semiconductor memory device and more particularly to a circuit for equalizing bit lines and / or input / output lines to increase the speed of input and

data output.

  As the semiconductor memory devices become highly integrated, the operating speed should be increased. The "read" and "write" operation of a semiconductor device is performed in such a way that memory cell transfers, and receives, data to and from the outside of a chip, via bit lines or data input / output lines that are connected between the memory cell and outside the chip In this case, the bit lines or the data input / output lines have an intrinsic load (i.e., line resistance, stray capacitance, etc.) which adversely affects data transfer This problem is very serious in a highly complex semiconductor memory device whose memory cells are smaller and whose operating voltage is lower In order to solve this problem he has A proposed method for equalizing bit lines or data input / output lines with respect to a source voltage level (Vcc) or half of it before the input / output operation data, which is described as shown in Figure 1 in an article titled "A 20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture" by Toshihiko Hirose, IEEE JOURNAL OF SOLID- STATE CIRCUITS, volume 25, number 5,

October 1990.

  Referring to FIGS. 1A and 1B which respectively represent the peripheral bit line circuit and the detection amplifiers, the signal SPGB which is the signal complementary to the signal SPG, is produced by the address transition detection circuit (ATD) to detect an external address transition, and the OBL Si signal is used to select one of the matrix blocks of

  memory containing a given memory cell.

  FIG. 2 is a chronogram of operation of the circuits of FIGS. 1A and 1B The operating characteristics of the circuits of FIGS. 1A and 1B are

described below.

  The transition from an external address is detected by the ATD circuit to produce the SPGB signal in the form of a short pulse The SPGB signal produces a BEQ signal in the form of a short pulse to equalize the bit lines BL, BLB and the I / O, I / OB input / output lines in the "high" level pulse interval, as shown in FIG. 2 Then the detection amplifiers S / A-1, S / A-2 rapidly detect the data from memory cell 20, as shown in FIG. 1 A The data read from memory cell 20 is transferred via a data output buffer means 40 to the outside the chip The bit lines BL, BLB and the input / output lines I / O and I / OB are preloaded with the source voltage level Vcc when the data read and write operation of the memory cell 20 is not executed, but they are equalized by the BEQ signal immediately before the operation memory cell data read and write ration The time during which the bit lines BL, BLB and the input / output lines I / O, I / OB are equalized depends on the size of the interval pulse o BEQ signal is "high" If bit lines BL, BLB and input / output lines I / O, I / OB have a relatively large intrinsic load, the interval of pulse must be increased to properly equalize the bit lines and the input / output lines Therefore, in the case of a semiconductor memory device of great complexity using a low operating voltage and very small memory cells (i.e., the size of the transistor making up the memory cell), the pulse interval should be increased, thereby causing a decrease in operating speed so that the data output is delayed In addition this causes the chip to function incorrectly e when the source voltage level Vcc

is weak.

  It is an objective of the present invention to propose a semiconductor memory device whose bit lines or data input / output lines

  are equalized without sacrificing operating speed.

  The present invention provides for this purpose a semiconductor memory device with an address transition detection circuit which comprises an input signal detector for receiving an externally input signal which is buffered in an input buffer for detecting a desired signal, control means for producing a signal for controlling a detection amplifier in response to the output signal from the input signal detector, and an equalization signal generator for producing an equalization signal for equalizing bit lines and data input / output lines by receiving the output signals from the input signal detector and the control means, whereby the bit lines and data input / output lines are always equalized for

  that the detection amplifier is not used.

  The characteristics and advantages of the invention

  will emerge from the description which follows,

  by way of example with reference to the accompanying drawings, in which: FIGS. 1A and 1B represent conventional circuits for equalizing the bit lines and the input / output lines with the detection amplifier; Figure 2 is a diagram showing a functional timing diagram of Figure 1; FIGS. 3 A and 3 B are block diagrams for representing a circuit for equalizing bit lines and input / output lines according to the present invention FIGS. 4 A to 4 C are detailed circuits for FIGS. 3 A and 3 B; Figure 5 is a diagram showing a functional timing diagram of Figures 3 A and 3 B; and FIG. 6 is the diagram of a functional timing diagram of the circuit of the invention compared to that of the

classic circuit.

  Referring to Fig. 3A, a block of memory cells from an array of memory cells "a" is connected via the bit lines BL, BLB or the input / output lines I / O , I / OB to a sense amplifier "b" An equalization circuit 50 is provided for equalizing the bit lines or the data input / output lines by an control signal Opzd A control amplifier signal SACS detection is applied to the detection amplifier "b" The equalization circuit 50 can be structured in various ways according to the prior art The circuit of FIG. 3 B is used to produce and control the signals Opzd and SACS A buffer memory 100 A input is conventionally obtained to buffer an external address, a control signal, etc. An input signal detector 100 B detects a desired signal from the output signal of the input buffer 100 A so as to produce an SPG detection signal A signal generator generator control signal 100 C receives the output signal from the input signal detector 100 B so as to produce a detection amplifier control signal SACS An equalization signal generator 100 D receives the output signals from the input signal detector 100 B and the detection amplifier control signal generator 100 C so as to produce the signal Opzd to equalize bit lines BL, BLB and data input / output lines

I / O, I / OB determined.

  Detailed circuits for making the blocks of FIG. 3 B are shown in FIGS. 4 A to 4 C. The input signal detector 100 B is shown in FIG. 4 A, the amplifier control signal generator 1 OOC to FIG. 4 B, and the equalization signal generator 100 D in FIG. 4 C The circuit of FIG. 4 A is a type of ATD circuit for detecting the transition of addresses

  input so as to produce an SPG detection signal.

  The chain of five cascaded inverters 101, 105 constitutes a delay circuit for producing the output signal SPG in the form of pulses when the transition from

input signal A Pl occurs.

  The OOC detection amplifier control signal generator, as shown in FIG. 4B, receives the signal SPG so as to produce the signal SACS in the form of short pulses when the signal SPG transitions from the "low" level. "at" high "Reference numeral 120 indicates a delay circuit (which will be described later) for delaying the SACS signal while the detection amplifier performs a detection operation. The equalization signal generator 100 D, as shown in FIG. 4 C, includes a NAND gate 121 for receiving the SPGB and SACS signals and for driving the inverters 122, 123 so as to produce the opzd signal to activate the equalization circuit 50 of FIG. 3 A. When the SACS signal is invalidated, the equalization circuit of FIG. 4 C produces continuously

  the signal opzd as validation signal of the "high" state.

  In operation, if no external address signal transition is entered (that is, the transition does not occur), the SPG signal is at "low" level (the SPGB signal being at " high "), the signal SACS is at the level" low ", and consequently the signal opzd is at the level" high ", so that the equalization circuit of figure 3 A is activated, thus equalizing the

  bit lines or data input / output lines.

  In this case, the read or write operation of the memory cell is not performed If an external address signal is entered (i.e. the transition occurs), the SPG signal is produced in the form of a short pulse of level "high" (the signal SPGB is produced in the form of a short pulse of level "low"), the signal SACS is of level "high", and consequently the signal Opzd is of "low" level after a delay time given by the delay circuit 120 of FIG. 4 B, so that the equalization circuit 50 is deactivated, thus stopping the equalization of the bit lines or of the lines d input / output while detection amplifier "b" is activated to detect data from memory cell So bit lines or data input / output lines are continuously equalized while amplifier is not implemented, and therefore the time taken for detection of the data in a determined memory cell becomes very short, as shown in FIG. 5 The detection operation has time to be performed while the SACS signal produced is of "high" level Then, if the interval d the pulse of the signal SPG ends, the signal SACS is again at the "low" level and the signal çpzd again at the "high" level, the equalization circuit 50 is again activated so as to equalize the bit lines or the data input / output lines immediately after the

  detection of the data of the memory cell.

  As shown in FIG. 6, the circuit of the invention reduces the detection time of the interval "T" compared to the conventional circuit, thus preventing the operating speed from being sacrificed taking into account the equalization of lines of bits and lines

data input / output.

  Although Figures 3 B, 4 A, 4 B, 4 C show a more preferred embodiment of the circuit of the invention, various modifications and changes with respect to it can be performed without departing from the spirit of the invention. The invention Of course, a person skilled in the art will readily appreciate that the circuit of Figure 3B can be effectively applied to only one or both of the bit lines or data input / output lines. As indicated above, the semiconductor memory device of the invention ensures that the bit lines and the data input / output lines connected to a determined amplifier are continuously equalized when the detection amplifier is not implemented, so that the operating speed is not degraded (which would cause erroneous operation of the chip) thereby ensuring the reliability of the device

semiconductor memory.

  Although the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be readily understood by those skilled in the art that modifications in form and in details can be made without go beyond the spirit and the field of the invention.

Claims (9)

  1 semiconductor memory device with an address transition detection circuit characterized in that it comprises: an input signal detection means (1 OOB) receiving a signal input from the outside (A Pi , A Pi B) which is buffered to detect a desired signal to produce a detection signal (SPG); control means (100 C) receiving said detection signal (SPG) from said input signal detection means (1 OB), for producing a control signal (SACS) for controlling a detection amplifier (b); and, an equalization signal generator means (1 OOD) receiving said output signals (SPG, SACS) from the input signal detection means (1 OOB) and the control means (100 C), for producing a equalization signal (Opzd) to equalize a pair of bit lines (BL, BLB) or data input / output lines (I / O, I / OB); whereby said pair of bit lines (BL, BLB) or pair of data input / output lines (I / O, I / OB) is always equalized while said amplifier   detection (b) is not implemented.   2 semiconductor memory device according to claim 1, characterized in that said pair of bit lines (BL, BLB) and said pair of data input / output lines (I / O, I / OB) are equalized by said equalization signal (Opzd).   3 semiconductor memory device according to claim 1, characterized in that said input signal detection means (1 OOB) comprises: a first delay means (101 to 105) producing an inverted input signal which is delayed; and means for producing said detection signal (SPG) with a logic level equal to that of said input signal (A Pi, A Pi B).   4 semiconductor memory device according to claim 3, characterized in that said first delay means (101 to 105) comprises an odd number of inverters. Semiconductor memory device according to claim 3, characterized in that said production means comprises: a NAND gate (106) receiving said input signal (A Pi) and said inverted input signal (A Pi B) ; and an inverter (107) for inverting the output of said NAND gate.   6 semiconductor memory device according to claim 1, characterized in that said control means (1 OOC) comprises: an inverter (111) for inverting said detection signal (SPG); second delay means (120) for delaying said reverse detection signal (SPGB) during reading or writing of data from a memory cell or in a memory cell in order to invalidate the output of said equalization signal generator means (100 D); and a NAND gate (114) for receiving the output of said second delay means (120) and said reverse detection signal (SPGB) to produce said control signal (SACS) with a logic level equal to that of said detection signal (SPG).   7 semiconductor memory device according to claim 6, characterized in that said second means   delay (120) includes an even number of reversers.   8 A semiconductor memory device according to claim 1, characterized in that said equalization signal generating means (100 D) comprises: an inverter means for inverting said detection signal (SPG); and a NAND gate (121) receiving the reverse detection signal (SPGB) from said reversing means and said control signal (SACS) to produce said equalization signal (lpzd) with a logic level complementary to that of said control signal (SACS).   9 Semiconductor memory device with an address transition detection circuit characterized in that it comprises: an input signal detection means (1 OOB) receiving a signal input from the outside (A Pi , A Pi B) which is buffered, to produce a detection signal (SPG) with a logic level equal to the logic level of said input signal; control means (100 C) receiving said detection signal (SPG) from said input signal detection means (1 00 B), for producing a control signal (SACS) with a logic level equal to said detection signal for controlling a detection amplifier (b); and, an equalization signal generating means (100 D) receiving said detection signal (SPG) and said control signal (SACS), for producing an equalization signal (Opzd) with a logic level complementary to said control signal to equalize a pair of bit lines (BL, BLB) and / or input / output lines (I / O, I / OB); whereby said pair of bit lines (BL, BLB) and / or input / output lines (I / O, I / OB) are always equalized before the data transfer operation is   executed by said sense amplifier (b).   10 Semiconductor memory device with a bit line peripheral circuit characterized in that it comprises: an input signal detection means (1 OOB) receiving a signal input from the outside (A Pi, A Pi B) which is buffered to produce a detection signal (SPG) with a logic level equal to the logic level of said input signal; control means (100 C) receiving said detection signal (SPG) from said input signal detection means (1 OOB), for producing a control signal (SACS) with a logic level equal to said detection signal for controlling a detection amplifier (b); and, an equalization signal generating means (100 D) receiving said detection signal (SPG) and said control signal (SACS), for producing an equalization signal (Opzd) with a logic level complementary to said control signal ; an equalization means receiving said equalization signal (Opzd) for controlling the equalization of said bit lines (BL, BLB) and / or said data input / output lines (I / O, I / OB), connecting said sense amplifier (b) and a memory array block (a); whereby said pair of bit lines (BL, BLB) and / or data input / output lines (I / O, I / OB) are always equalized before the data transfer operation, from of said memory array block, or   executed by said sense amplifier (b).