CN1072528A - 提高半导体存贮器的操作速度的电路 - Google Patents

提高半导体存贮器的操作速度的电路 Download PDF

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Publication number
CN1072528A
CN1072528A CN92113235A CN92113235A CN1072528A CN 1072528 A CN1072528 A CN 1072528A CN 92113235 A CN92113235 A CN 92113235A CN 92113235 A CN92113235 A CN 92113235A CN 1072528 A CN1072528 A CN 1072528A
Authority
CN
China
Prior art keywords
signal
input
detection
control
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN92113235A
Other languages
English (en)
Chinese (zh)
Inventor
李炯坤
张喆雄
赵星熙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN1072528A publication Critical patent/CN1072528A/zh
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
CN92113235A 1991-11-19 1992-11-19 提高半导体存贮器的操作速度的电路 Pending CN1072528A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019910020595A KR930010990A (ko) 1991-11-19 1991-11-19 반도체 메모리 장치에서의 스피드 향상을 위한 회로
KR20595/91 1991-11-19

Publications (1)

Publication Number Publication Date
CN1072528A true CN1072528A (zh) 1993-05-26

Family

ID=19323071

Family Applications (1)

Application Number Title Priority Date Filing Date
CN92113235A Pending CN1072528A (zh) 1991-11-19 1992-11-19 提高半导体存贮器的操作速度的电路

Country Status (8)

Country Link
JP (1) JPH05217378A (enrdf_load_stackoverflow)
KR (1) KR930010990A (enrdf_load_stackoverflow)
CN (1) CN1072528A (enrdf_load_stackoverflow)
DE (1) DE4234153A1 (enrdf_load_stackoverflow)
FR (1) FR2683934A1 (enrdf_load_stackoverflow)
GB (1) GB2261754A (enrdf_load_stackoverflow)
IT (1) IT1258253B (enrdf_load_stackoverflow)
TW (1) TW198157B (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102723100A (zh) * 2012-05-23 2012-10-10 常州芯奇微电子科技有限公司 多功能内存接口电路
CN103098136A (zh) * 2010-08-13 2013-05-08 美光科技公司 线路终止方法及设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940002860A (ko) * 1992-07-27 1994-02-19 김광호 어드레스 변동 검출기

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6224875A (ja) * 1985-07-24 1987-02-02 Sekisui Chem Co Ltd 溶接装置
JPH0640439B2 (ja) * 1986-02-17 1994-05-25 日本電気株式会社 半導体記憶装置
JPH07107797B2 (ja) * 1987-02-10 1995-11-15 三菱電機株式会社 ダイナミツクランダムアクセスメモリ
KR910003605B1 (ko) * 1988-04-30 1991-06-07 삼성전자 주식회사 Sram 센스앰프의 등화회로
JPH0814989B2 (ja) * 1989-05-09 1996-02-14 日本電気株式会社 内部同期型スタティックｒａｍ
US4969125A (en) * 1989-06-23 1990-11-06 International Business Machines Corporation Asynchronous segmented precharge architecture
EP0419852A3 (en) * 1989-09-22 1992-08-05 Texas Instruments Incorporated A memory with selective address transition detection for cache operation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103098136A (zh) * 2010-08-13 2013-05-08 美光科技公司 线路终止方法及设备
CN103098136B (zh) * 2010-08-13 2016-07-06 美光科技公司 线路终止方法及设备
US12235760B2 (en) 2010-08-13 2025-02-25 Lodestar Licensing Group Llc Apparatus having selectively-activated termination circuitry
CN102723100A (zh) * 2012-05-23 2012-10-10 常州芯奇微电子科技有限公司 多功能内存接口电路

Also Published As

Publication number Publication date
IT1258253B (it) 1996-02-22
ITMI922575A0 (it) 1992-11-10
GB2261754A (en) 1993-05-26
KR930010990A (ko) 1993-06-23
ITMI922575A1 (it) 1994-05-10
TW198157B (enrdf_load_stackoverflow) 1993-01-11
GB9224303D0 (en) 1993-01-06
JPH05217378A (ja) 1993-08-27
DE4234153A1 (de) 1993-05-27
FR2683934A1 (fr) 1993-05-21

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C06 Publication
PB01 Publication
C01 Deemed withdrawal of patent application (patent law 1993)
WD01 Invention patent application deemed withdrawn after publication