FR2667981A1 - Procede d'assemblage de deux couches constituees de materiaux differents et son application a l'encapsulation hermetique de circuits hybrides. - Google Patents

Procede d'assemblage de deux couches constituees de materiaux differents et son application a l'encapsulation hermetique de circuits hybrides. Download PDF

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Publication number
FR2667981A1
FR2667981A1 FR9012607A FR9012607A FR2667981A1 FR 2667981 A1 FR2667981 A1 FR 2667981A1 FR 9012607 A FR9012607 A FR 9012607A FR 9012607 A FR9012607 A FR 9012607A FR 2667981 A1 FR2667981 A1 FR 2667981A1
Authority
FR
France
Prior art keywords
layer
screen printing
dielectric
mixture
assembling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR9012607A
Other languages
English (en)
French (fr)
Other versions
FR2667981B1 (enExample
Inventor
De Reynal Florence
Goujard Dominique
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR9012607A priority Critical patent/FR2667981A1/fr
Priority to EP91402675A priority patent/EP0481846A1/fr
Priority to JP3290921A priority patent/JPH04280654A/ja
Priority to US07/774,346 priority patent/US5201456A/en
Publication of FR2667981A1 publication Critical patent/FR2667981A1/fr
Application granted granted Critical
Publication of FR2667981B1 publication Critical patent/FR2667981B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Ceramic Products (AREA)
  • Casings For Electric Apparatus (AREA)
  • Manufacturing Of Printed Wiring (AREA)
FR9012607A 1990-10-12 1990-10-12 Procede d'assemblage de deux couches constituees de materiaux differents et son application a l'encapsulation hermetique de circuits hybrides. Granted FR2667981A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR9012607A FR2667981A1 (fr) 1990-10-12 1990-10-12 Procede d'assemblage de deux couches constituees de materiaux differents et son application a l'encapsulation hermetique de circuits hybrides.
EP91402675A EP0481846A1 (fr) 1990-10-12 1991-10-08 Procédé d'assemblage d'un capot métallique sur un substrat portant un circuit intégré
JP3290921A JPH04280654A (ja) 1990-10-12 1991-10-09 集積回路を有する基板上への金属容器の組立て法
US07/774,346 US5201456A (en) 1990-10-12 1991-10-10 Process for assembly of a metal can on a substrate bearing an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9012607A FR2667981A1 (fr) 1990-10-12 1990-10-12 Procede d'assemblage de deux couches constituees de materiaux differents et son application a l'encapsulation hermetique de circuits hybrides.

Publications (2)

Publication Number Publication Date
FR2667981A1 true FR2667981A1 (fr) 1992-04-17
FR2667981B1 FR2667981B1 (enExample) 1997-02-28

Family

ID=9401166

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9012607A Granted FR2667981A1 (fr) 1990-10-12 1990-10-12 Procede d'assemblage de deux couches constituees de materiaux differents et son application a l'encapsulation hermetique de circuits hybrides.

Country Status (4)

Country Link
US (1) US5201456A (enExample)
EP (1) EP0481846A1 (enExample)
JP (1) JPH04280654A (enExample)
FR (1) FR2667981A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2758630B1 (fr) * 1997-01-21 1999-04-09 Thomson Tubes Electroniques Procede de scellement etanche d'un detecteur de rayonnement a l'etat solide et detecteur obtenu par ce procede
US6136128A (en) * 1998-06-23 2000-10-24 Amerasia International Technology, Inc. Method of making an adhesive preform lid for electronic devices
US6342407B1 (en) 2000-12-07 2002-01-29 International Business Machines Corporation Low stress hermetic seal
US7743963B1 (en) 2005-03-01 2010-06-29 Amerasia International Technology, Inc. Solderable lid or cover for an electronic circuit
CN118750586A (zh) 2017-04-06 2024-10-11 莎思坦控股有限责任公司 基于胶原的药物组合物和装置和生产方法及其用途
WO2020219486A2 (en) 2019-04-22 2020-10-29 Sustain Holdings, Llc Collagen peptide-based medicament compositions and devices and methods of production and use thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1431919A (en) * 1973-08-15 1976-04-14 Atomic Energy Authority Uk Microcircuit packages
GB1468973A (en) * 1975-07-18 1977-03-30 Atomic Energy Authority Uk Microcircuit packages
JPS60110156A (ja) * 1983-11-21 1985-06-15 Hitachi Ltd 固体撮像素子の製造方法
EP0178481A2 (en) * 1984-09-19 1986-04-23 Olin Corporation Hermetically sealed semiconductor package
JPS61193473A (ja) * 1985-02-21 1986-08-27 Fujitsu Ltd 積層回路基板のピンリ−ド
JPS62241356A (ja) * 1986-04-14 1987-10-22 Hitachi Ltd 半導体パツケ−ジ
US4704626A (en) * 1985-07-08 1987-11-03 Olin Corporation Graded sealing systems for semiconductor package

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3020182A (en) * 1958-09-26 1962-02-06 Gen Electric Ceramic-to-metal seal and method of making the same
US4338380A (en) * 1976-04-05 1982-07-06 Brunswick Corporation Method of attaching ceramics to metals for high temperature operation and laminated composite

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1431919A (en) * 1973-08-15 1976-04-14 Atomic Energy Authority Uk Microcircuit packages
GB1468973A (en) * 1975-07-18 1977-03-30 Atomic Energy Authority Uk Microcircuit packages
JPS60110156A (ja) * 1983-11-21 1985-06-15 Hitachi Ltd 固体撮像素子の製造方法
EP0178481A2 (en) * 1984-09-19 1986-04-23 Olin Corporation Hermetically sealed semiconductor package
JPS61193473A (ja) * 1985-02-21 1986-08-27 Fujitsu Ltd 積層回路基板のピンリ−ド
US4704626A (en) * 1985-07-08 1987-11-03 Olin Corporation Graded sealing systems for semiconductor package
JPS62241356A (ja) * 1986-04-14 1987-10-22 Hitachi Ltd 半導体パツケ−ジ

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 009, no. 263 (E-351) 19 octobre 1985, & JP-A-60 110156 (HITACHI SEISAKUSHO KK) 15 juin 1985, *
PATENT ABSTRACTS OF JAPAN vol. 011, no. 023 (E-473) 22 janvier 1987, & JP-A-61 193473 (FUJITSU LTD.) 27 août 1986, *
PATENT ABSTRACTS OF JAPAN vol. 012, no. 111 (E-598) 08 avril 1988, & JP-A-62 241356 (HITACHI LTD.) 22 octobre 1987, *

Also Published As

Publication number Publication date
JPH04280654A (ja) 1992-10-06
FR2667981B1 (enExample) 1997-02-28
EP0481846A1 (fr) 1992-04-22
US5201456A (en) 1993-04-13

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