FR2451615A1 - Memoire a semi-conducteurs comportant des cellules a un transistor realisees suivant la technologie v-mos - Google Patents
Memoire a semi-conducteurs comportant des cellules a un transistor realisees suivant la technologie v-mosInfo
- Publication number
- FR2451615A1 FR2451615A1 FR8005046A FR8005046A FR2451615A1 FR 2451615 A1 FR2451615 A1 FR 2451615A1 FR 8005046 A FR8005046 A FR 8005046A FR 8005046 A FR8005046 A FR 8005046A FR 2451615 A1 FR2451615 A1 FR 2451615A1
- Authority
- FR
- France
- Prior art keywords
- zones
- semiconductor memory
- mos technology
- cells
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 101150068246 V-MOS gene Proteins 0.000 title abstract 2
- 239000004020 conductor Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
MEMOIRE A SEMI-CONDUCTEURS COMPORTANT DES CELLULES A UN TRANSISTOR REALISEES SUIVANT LA TECHNOLOGIE V-MOS. DANS CETTE MEMOIRE COMPORTANT DES ZONES ENSEVELIES PREVUES SELON UNE SUCCESSION DE COUCHES CONSTITUEES PAR UN SUBSTRAT SEMI-CONDUCTEUR 1, UNE COUCHE EPITAXIALE 3 ET UNE ZONE ENSEVELIE 2 ET DES SILLONS 5 EN FORME DE V, LES ZONES ENSEVELIES 2 FORMANT DES CONDUCTEURS DE BITS ET DES ZONES D'UN TYPE DE CONDUCTIVITE OPPOSE DANS LA COUCHE 3, ENGLOBENT POUR CHAQUE CELLULE DE MEMOIRE, DES ZONES PARTIELLES 34-1, 34-2 SEPAREES PAR LE SILLON 5 FORMANT DES CAPACITES PARTIELLES BRANCHEES EN PARALLELE DES CELLULES DE MEMOIRE. APPLICATION NOTAMMENT AUX MEMOIRES A DES CELLULES A UN TRANSISTOR.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19792909820 DE2909820A1 (de) | 1979-03-13 | 1979-03-13 | Halbleiterspeicher mit eintransistorzellen in v-mos-technologie |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2451615A1 true FR2451615A1 (fr) | 1980-10-10 |
Family
ID=6065259
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8005046A Withdrawn FR2451615A1 (fr) | 1979-03-13 | 1980-03-06 | Memoire a semi-conducteurs comportant des cellules a un transistor realisees suivant la technologie v-mos |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS55125668A (fr) |
DE (1) | DE2909820A1 (fr) |
FR (1) | FR2451615A1 (fr) |
GB (1) | GB2044997A (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59161860A (ja) * | 1983-03-07 | 1984-09-12 | Hitachi Ltd | 半導体メモリ装置 |
JPS60257560A (ja) * | 1984-06-04 | 1985-12-19 | Mitsubishi Electric Corp | 半導体メモリ装置 |
US4651183A (en) * | 1984-06-28 | 1987-03-17 | International Business Machines Corporation | High density one device memory cell arrays |
JPH0793365B2 (ja) * | 1984-09-11 | 1995-10-09 | 株式会社東芝 | 半導体記憶装置およびその製造方法 |
US5204281A (en) * | 1990-09-04 | 1993-04-20 | Motorola, Inc. | Method of making dynamic random access memory cell having a trench capacitor |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4003036A (en) * | 1975-10-23 | 1977-01-11 | American Micro-Systems, Inc. | Single IGFET memory cell with buried storage element |
FR2379134A1 (fr) * | 1977-01-31 | 1978-08-25 | Siemens Ag | Memoire a semi-conducteurs |
GB2011175A (en) * | 1977-12-27 | 1979-07-04 | American Micro Syst | Improvements in or relating to a semiconductor device |
-
1979
- 1979-03-13 DE DE19792909820 patent/DE2909820A1/de not_active Withdrawn
-
1980
- 1980-03-06 FR FR8005046A patent/FR2451615A1/fr not_active Withdrawn
- 1980-03-11 GB GB8008260A patent/GB2044997A/en not_active Withdrawn
- 1980-03-11 JP JP3083880A patent/JPS55125668A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4003036A (en) * | 1975-10-23 | 1977-01-11 | American Micro-Systems, Inc. | Single IGFET memory cell with buried storage element |
FR2379134A1 (fr) * | 1977-01-31 | 1978-08-25 | Siemens Ag | Memoire a semi-conducteurs |
GB2011175A (en) * | 1977-12-27 | 1979-07-04 | American Micro Syst | Improvements in or relating to a semiconductor device |
FR2413789A1 (fr) * | 1977-12-27 | 1979-07-27 | American Micro Syst | Dispositif de memoire a semi-conducteurs |
Non-Patent Citations (2)
Title |
---|
EXBK/77 * |
EXBK/78 * |
Also Published As
Publication number | Publication date |
---|---|
JPS55125668A (en) | 1980-09-27 |
DE2909820A1 (de) | 1980-09-18 |
GB2044997A (en) | 1980-10-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |