FR2413789A1 - Dispositif de memoire a semi-conducteurs - Google Patents

Dispositif de memoire a semi-conducteurs

Info

Publication number
FR2413789A1
FR2413789A1 FR7829050A FR7829050A FR2413789A1 FR 2413789 A1 FR2413789 A1 FR 2413789A1 FR 7829050 A FR7829050 A FR 7829050A FR 7829050 A FR7829050 A FR 7829050A FR 2413789 A1 FR2413789 A1 FR 2413789A1
Authority
FR
France
Prior art keywords
recess
line
buried
semiconductor memory
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7829050A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
American Microsystems Holding Corp
Original Assignee
American Microsystems Holding Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Microsystems Holding Corp filed Critical American Microsystems Holding Corp
Publication of FR2413789A1 publication Critical patent/FR2413789A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/35—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

LE DISPOSITIF DE MEMOIRE A SEMI-CONDUCTEURS DE L'INVENTION COMPREND UN SUBSTRAT 18 SUPPORTANT UN AGENCEMENT DE CELLULES DE MEMOIRE DANS LEQUEL CHAQUE CELLULE COMPREND UN EVIDEMENT EN FORME DE V DONT L'EXTREMITE INFERIEURE PENETRE DANS UNE LIGNE DE BITS 16 "ENTERREE" DANS LE SUBSTRAT 18. LES LIGNES DE MOTS 14 PARALLELES ET ESPACEES, EN MATIERE CONDUCTRICE, FORMEES SUR LA SURFACE DU DISPOSITIF PERPENDICULAIREMENT AUX LIGNES DE BITS S'ETENDENT JUSQUE DANS LES EVIDEMENTS DES CELLULES DE MEMOIRE. POUR CHAQUE EVIDEMENT, UNE BARRIERE DE SEUIL 20 AUTOUR DE SON EXTREMITE SUPERIEURE ET UNE BARRIERE DE DIFFUSION 22 AUTOUR DE SON EXTREMITE INFERIEURE ADJACENTE A LA LIGNE DE BITS "ENTERREE" SE COMBINENT DE MANIERE A FORMER UNE ZONE D'EMMAGASINAGE DE CHARGE DANS LA MATIERE FORMANT LES PAROIS DE L'EVIDEMENT DE SORTE QUE LA PARTIE D'UNE LIGNE DE MOTS A L'INTERIEUR DE CHAQUE EVIDEMENT CONSTITUE UNE GRILLE POUR MODULER LA CIRCULATION DE LA CHARGE VERS ET DEPUIS LA LIGNE DE BITS PENDANT LES OPERATIONS DE LECTURE ET D'ECRITURE.
FR7829050A 1977-12-27 1978-10-11 Dispositif de memoire a semi-conducteurs Withdrawn FR2413789A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US86453677A 1977-12-27 1977-12-27

Publications (1)

Publication Number Publication Date
FR2413789A1 true FR2413789A1 (fr) 1979-07-27

Family

ID=25343489

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7829050A Withdrawn FR2413789A1 (fr) 1977-12-27 1978-10-11 Dispositif de memoire a semi-conducteurs

Country Status (7)

Country Link
JP (1) JPS5492077A (fr)
CA (1) CA1118892A (fr)
DE (1) DE2842334A1 (fr)
FR (1) FR2413789A1 (fr)
GB (1) GB2011175B (fr)
IT (1) IT7869937A0 (fr)
NL (1) NL7808079A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2451615A1 (fr) * 1979-03-13 1980-10-10 Siemens Ag Memoire a semi-conducteurs comportant des cellules a un transistor realisees suivant la technologie v-mos

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4252579A (en) * 1979-05-07 1981-02-24 International Business Machines Corporation Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition
US4335450A (en) * 1980-01-30 1982-06-15 International Business Machines Corporation Non-destructive read out field effect transistor memory cell system
US4423490A (en) * 1980-10-27 1983-12-27 Burroughs Corporation JFET Dynamic memory
JPS6135554A (ja) * 1984-07-28 1986-02-20 Nippon Telegr & Teleph Corp <Ntt> 読出し専用メモリ−およびその製造方法
US4997783A (en) * 1987-07-02 1991-03-05 Integrated Device Technology, Inc. Static ram cell with trench pull-down transistors and buried-layer ground plate
US4987090A (en) * 1987-07-02 1991-01-22 Integrated Device Technology, Inc. Static ram cell with trench pull-down transistors and buried-layer ground plate
US6963108B1 (en) * 2003-10-10 2005-11-08 Advanced Micro Devices, Inc. Recessed channel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2451615A1 (fr) * 1979-03-13 1980-10-10 Siemens Ag Memoire a semi-conducteurs comportant des cellules a un transistor realisees suivant la technologie v-mos

Also Published As

Publication number Publication date
GB2011175B (en) 1982-02-10
IT7869937A0 (it) 1978-12-22
CA1118892A (fr) 1982-02-23
GB2011175A (en) 1979-07-04
NL7808079A (nl) 1979-06-29
JPS5492077A (en) 1979-07-20
DE2842334A1 (de) 1979-07-05

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Legal Events

Date Code Title Description
ST Notification of lapse