GB2044997A - A semiconductor store comprising one-transistor storage cells formed by V-MOS Technology - Google Patents
A semiconductor store comprising one-transistor storage cells formed by V-MOS Technology Download PDFInfo
- Publication number
- GB2044997A GB2044997A GB8008260A GB8008260A GB2044997A GB 2044997 A GB2044997 A GB 2044997A GB 8008260 A GB8008260 A GB 8008260A GB 8008260 A GB8008260 A GB 8008260A GB 2044997 A GB2044997 A GB 2044997A
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- United Kingdom
- Prior art keywords
- layer
- store
- zones
- trench
- semiconductor
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 210000000352 storage cell Anatomy 0.000 title claims abstract description 26
- 238000005516 engineering process Methods 0.000 title claims abstract description 5
- 101150068246 V-MOS gene Proteins 0.000 title claims description 4
- 210000004027 cell Anatomy 0.000 claims abstract description 33
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 238000009413 insulation Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010276 construction Methods 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
A semiconductor store comprises a plurality of one-transistor storage cells formed by V-MOS-technology, each cell comprising a buried-layer zone (2) formed in and of the opposite conductivity type to a layer sequence consisting of a semiconductor substrate (1) and an epitaxial layer (3) thereon; a further zone of the opposite conductivity type formed in the surface of the epitaxial layer (3) and divided into at least two separate sub-zones (4.1, 4.2) by a V-shaped trench (5), which extends into the buried-layer zone (2); an insulating layer (6) on the surface of the epitaxial layer (3) which in the trench (5) forms the gate insulation (6.1, 6.2) of a V-MOS-transistor; and a conductor path (7) on the insulating layer (6) which in the trench (5) forms the gate electrode of the V-MOS-transistor. The buried-layer zone (2) serves as a bit line and preferably runs in the column direction of the store, the conductor path (7) forms a word line and preferably runs in the row direction of the store, whilst the sub-zones (4.1, 4.2) form parallel- connected partial capacitances of the storage cell, so that if one of the partial capacitances should breakdown, at least one other partial capacitance will remain effective and total breakdown of the store is avoided. The sub-zones (4.1, 4.2) in the surface of the epitaxial layer may be formed by diffusion or by field-induction due to a floating electrode (31). <IMAGE>
Description
SPECIFICATION
A semiconductor store comprising one-transistor cells formed by v-mos-technology
The present invention relates to a semiconductor store comprising one-transistor cells formed by
V-MOS-technology.
Stores of this kind are known in which each storage cell comprises a buried-layer zone arranged in a layer sequence consisting of a semiconductor substrate and an epitaxial layer located thereupon, the buried-layer zone being of the opposite conductivity type to that of the semiconductor substrate and the epitaxial layer (which are the same); a further zone of the opposite conductivity type arranged in the surface of the epitaxial layer, a V-shaped trench extending through the further zone of the opposite conductivity into the epitaxial layer and the buriedlayer zone, at least one insulating layer covering the surface of the epitaxial layer including the exposed surfaces of the V-shaped trench which insulating layer forms the gate-insulator of an MOS-transistor in the V-shaped trench, and a conductor path extending into the V-shaped trench and serving as a word line, the word line preferably running in the row-direction of the store.
Semiconductor stores of this kind have been described in "Digest of technical Papers" of the IEEE
International Solid-State Circuits Conference 1978, at pages 156 and 157. In these known semiconductor stores, the buried-layer zones form the storage capacitances of th one-transistor cells, whilst the further zones of the opposite conductivity type which are located in the epitaxial layer and through which the V-shaped trenches extend at the locations of the V-MOS-transistors, form the bit-lines of the semiconductor store.
A disadvantage of such a storage configuration is that, with a given storage cell size, in order to achieve a high packing density the buried-layer zones which form the cell capacitances cannot be enlarged at will, so that the value of the storage cell capacitance is limited. A further disadvantage is that, in the event of the breakdown of one storage cell capacitance due to production defects which usually cannot be eliminated, the overall store becomes useless.
It is an object of the present invention to provide a semiconductor store of the general kind referred to above having a redudant storage cell capacitance so that the probability of the complete breakdown of a storage cell capacitance is substantially reduced.
According to the invention, there is provided a semi-conductor store comprising a plurality of onetransistor storage cells formed by V-MOStechnology in a layer sequence consisting of a semiconductor substrate of one conductivity type and an epitaxial layer thereon of the same conductivitytype, each said cell comprising a buried-layer zone arranged in said layer sequence and of the opposite conductivity type thereto; a further zone of the opposite conductivity type thereto; a further zone of the opposite conductivity type to that of the epitaxial layer located in the surface of said epitaxial zone and divided into at least two separate subzones by a V-shaped trench in the surface of the epitaxial layer and which trench extends into said buried-layer zone; at least one insulating layer covering the surface of said epitaxial layer including the surface exposed in said trench and forming in said trench the gate insulation of a V-MOS transistor; and a conductor path located on the surface of said insulating layer and forming the gate of said
V-MOS transistor within said trench; said buriedlayer zone serving as a bit line of said store, said conductor path serving as a word line of said store, and said sub-zones together forming paralielconnected partical capacitances of the storage capacitance of said storage cell. Preferably, the conductor paths forming the word lines run in the row direction and the buried-layer zones forming the bit lines run in the column direction of the store.
The semiconductor store of the invention thus has the advantage that, in the event of the breakdown of one partial capacitance formed by the sub-zones of the further zone, at least one other partial capacitance will still remain effective, so that this particular storage location, and thus the entire store, does not completely break down.
The sub-zones of the opposite conductivity type formed in the surface of the epitaxial layer on either side of the V-shaped trench, may be in the form of diffused zones in the surface of the epitaxial layer, or they may be formed by field induction on MOScapacitances.
Two sub-zones of the opposite conductivity type to that of the epitaxial layer may be formed separated by the V-shaped trench, in which case the sub-zones preferably lie in the row direction of the store. Alternatively four such sub-zones may be provided, in which case they are preferably arranged in the form of a cross and extend in both the row and column directions.
The invention will now be further described with reference to the drawings, in which:
Figures 1 to 6 illustrate successive stages in the production of a first form of storage cell for use in a store in accordance with the invention, Figures 2, 4 and 6 being schematic plan views of part of a semiconductor body at successive production stages and Figures 1, 3 and 6 being sections taken along the lines l-l, Ill-Ill and V-V of Figures 2, 4 and 6 respectively;
Figure 7 is an equivalent circuit diagram of a storage cell of Figures 5 and 6;
Figure 8 is a schematic plan view of a second form of storage cell for use in a semiconductor store in accordance with the invention;
Figure 9 is an equivalent circuit diagram of the storage cell of Figure 8;;
Figure 10 is a schematic plan view of part of a semiconductor store comprising storage cells in accordance with Figure 8;
Figure 11 is a schematic side sectional view of part of a semiconductor body to illustrate a stage in an alternative method of producing a storage cell as shown in Figures 5 and 6, the section being taken along the line Xl-Xl of Figure 12;
Figure 12 is a schematic plan view of the semicon ductor body shown in Figure 11; and
Figure 13 is a schematic side sectional view of a further form of storage cell for use in a store in accordance with the invention.
In the form of storage cell, the production of which is illustrated in Figures 1 to 6 of the drawings, the starting point as a semiconductor substrate 1 which consists in the usual way of silicon and in the example under consideration is assumed to have p-conductivity.
A highly doped longitudinally-extending buriedlayer zone 2 of the opposite conductivity type, i.e.
having n±conductivity, and an epitaxial layer 3 which also possesses p-conductivity are produced in conventional fashion. A highly doped zone 4 of the opposite conductivity type, i.e. a n±zone, is produced in the surface of the epitaxial layer 3, for example, by diffusion, the zone 4 lying above the buried-layer zone 2, as shown in the plan view of
Figure 2, which also shows the shapes and directions of the zones 2 and 4.
In a further step, a V-shaped trench 5 which, as shown in Figure 3, divides the zone 4 into two sub-zones 4.1 and 4.2 respectively and extends into the buried-layerzone 2 through the epitaxial layer 3, is produced by ansitropic etching.
As shown in Figure 5, an insulating layer 6 which in the V-shaped trench 5 represents the gate insulation 6.1. of a V-MOS-transistor of a one-transistor cell formed in the trench 5, and which in conventional manner consists of silicon dioxide, is subsequently deposited onto the surface of the arrangement of
Figure 3. A metal layer 7 which forms the gate electrode of the V-MOS-transistor of the onetransistor cell in the V-shaped trench is then applied on the insulating layer 6, 6.1. A plan view of the finished structure of Figure 5 is shown in Figure 6.
In accordance with the invention, the continuous buried-layer zone 2 (as shown in the plan views of
Figures 2, 4 and 6) forms a bit line of the store, whilst the sub-zones 4.1 and 4.2 which are separated by the
V-shaped trench 5 and are of the opposite conductivity type to that of the epitaxial layer 3 form respective partial storage capacitances of the one-transistor cell. As already mentioned the metal layer 7, which usually consists of aluminum, forms the gate electrode of the V-MOS-transistor of the one-transistor cell located in the V-shaped trench, and also forms a word line of one row of one-transistor cells. The other one-transistor cells of the store which are not shown, have an identical construction to the cell illustrated in Figures 5 and 6.
Figure 7 is an equivalent circuit diagram of a one-transistor cell in accordance with Figure 5. In this diagram the transistor T represents the V-MOStransistor whilst two capacitances C1 and C2 represent the partial capacitances which are formed by the zones 4.1 and 4.2 respectively of the arrangement of Figure 5. The bit line 2 is arranged on the source-drain path of the T, whilst the word line forms the gate of this transistor.
It should be pointed out that the illustrations of
Figures 5 and 6 are only schematic representations which serve to clarify the arrangement of the bit line and the storage capacitances of the one-transistor cells. Otherwise, the construction of a storage cell of this kind is of conventional type and is described, for example, in the publication previously referred to.
Figure 8 illustrates a further form of one-transistor cell for use in a semiconductor store in accordance with the invention, in which four partial storage capacitances 4.1,4.2,4.3 and 4.4 are present in place of the two partial storage capacitances of the cell shown in Figures 5 and 6. Again a diffused zone of the opposite conductivity type to that of the epitaxial layer can be provided which is divided into four sub-zones by the V-shaped trench 5. As can be seen from Figure 8, these sub-zones are arranged in the form of a cross.
It can be seen from the equivalent circuit diagram of Figure 9 that four partial capacitances C1, C2, C3 and C4 result from the use of an arrangement in accordance with Figure 8.
Figure 10 shows a part of a semiconductor store comprising a plurality of one-transistor cells in accordance with Figure 8 and which illustrate the relative arrangement of the one-transistor cells to one another in the store. A part of a store comprising five bit lines 2-N,2-N+1,....2-N+5 and three word lines 7-N, 7-N+1 and 7-N +2 is illustrated. It will be seen that the sub-zones 4.1,4.2,4.3 and 4.4 extend in both the row and column directions.
Figures 11 and 12 illustrate an arrangement corresponding to that of Figures 1 to 6 in which the zone which forms the partial capacitances in the completed cell is not initially produced as a continuous zone as in Figure 1, but in the form of two separate zones 4.10 and 4.11, which may, for example, be diffused zones. Otherwise, the further production of the cell corresponds to stages illustrated in Figures 1 to6.
Figure 13 illustrates a further form of a onetransistor cell forming part of a semiconductor store in accordance with the invention, in which the partial capacitances of the cell are produced by MOScapacitors.
So far as the substrate 1, the buried-layer zone 2 which forms the bit line, the epitaxial layer 3 and the
V-shaped trench 5 are conerned, the arrangement of
Figure 13 corresponds to the forms of cell illustrated in Figures 1 to 12.
In order to produce the MOS-capacitors, a first insulating layer 30 which, as usual, consists of silicon dioxide and possesses thick-oxide regions 30' is applied onto the structure already produced including the surface of the V-shaped trenches 5. The thick-oxide regions 30' serve to insulate the individual storage cells from one another. In the Vshaped trench 5, this first insulating layer 30 forms the gate-oxide insulation 30.1 of the V-MOStransistor of the one-transistor cell.
A first layer 31 consisting of conductive material (preferably polycrystalline silicon) is applied onto the first insulating layer 30,30' on each side of the
V-shaped trench 5 but outside the trench. Subsequently, a second insulating layer 32 which consists in the conventional way of silicon dioxide, is applied over the whole arrangement, this layer being connected to the first insulating layer 30 at the mouth of the V-shaped trench 5. This layer 32 serves to insulate the conductive layers 31 from a second layer of conductive material, preferably aluminium, which is applied onto the second insulating layer 32 and the gate-insulation 30.1. This second layer 33 of conductive material forms the gate-electrode of the
V-MOS-transistor of the one-transistor cell formed in the V-shaped trench 5 and also the word line of a storage row.
As a result of the arrangement described above,
MOS-transistors which include depletion zones 34.1 and 34.2 and act as charge storage capacitances in the one-transistor cell are formed in the epitaxial layer adjacent to the V-MOS-transistor in the Vshaped trench 5. In this form of cell, the zones 34.1 and 34.2 again form partial capacitances as with the corresponding sub-zones of the cells illustrted in
Figures 1 to 12; however, these zones are not formed by doping but by field induction.
Claims (12)
1. A semiconductor store comprising a plurality of one-transistor storage cells formed by V-MOS technology in a layer sequence consisting of a semiconductor substrate of one conductivity type and an epitaxial layer thereon of the same conductivitytype, each said cell comprising a buried-layer zone arranged in said layer sequence and of the opposite conductivity type thereto; a further zone of the opposite conductivity type to that of the epitaxial layer located in the surface of said epitaxial zone and divided into at least two separate sub-zones by a
V-shaped trench in the surface of the epitaxial layer and which trench extends into said buried-layer zone at least one insulating layer covering the surface of said epitaxial layer including the surface exposed in said trench and forming in said trench the gate insulation of a V-MOS-transistor; and a conductor path located on the surface of said insulating layer and forming the gate of said V-MOS-transistor within said trench; said buried-layer zone serving as a bit line of said store, said conductor path serving as a word line of said store, and said sub-zones together forming parallel-connected partial capacitances of the storage capacitance of said storage cell.
2. A semiconductor store as claimed in Claim 1, wherein for each cell, said buried-layer zone runs in the column direction of the store and forms part of a common bit line of all the storage cells in one column, and said conductor path runs in the row direction of the store and forms part of a common word line of all the storage cells in one row.
3. A semiconductor store as claimed in Claim 1 or Claim 2, wherein each of said sub-zones of the opposite conductivity type to that of said epitaxial layer are doped zones.
4. A semiconductor store as claimed in any one of Claims 1 to 3, wherein in each cell, two said sub-zones separated by the V-shaped trench are arranged in the epitaxial layer.
5. A semiconductor store as claimed in Claim 3, wherein said sub-zones extend on either side of said
V-shaped trench in the row direction of said store.
6. A semiconductor store as claimed in any one of Claims 1 to 3, wherein, in each cell, four said sub-zones separated by the V-shaped trench, are arranged in said epitaxial layer.
7. A semiconductor store as claimed in Claim 6, wherein said sub-zones are arranged in the form of a cross and extend in both the row and column directions of the store.
8. A semiconductor store as claimed in Claim 1, or Claim 2, wherein there is arranged on the surface of the epitaxial layer including the surface exposed in said V-shaped trench a first insulating layer which forms the gate-insulation of the MOS-transistor of the storage cell in the V-shaped trench a first layer of electrically conductive material is arranged on said first insulating layer outside said V-shaped trench, a second insulating layer is arranged to cover said first layer of electrically conductive material and is connected to said first insulating layer at the mouth of said trench, and a second continuous layer of electrically conductive material is applied to the layer structure consisting of said first insulating layer, said first layer of electrically conductive material and said second insulating layer to form said conductor path serving as a word line and as the gate electrode of the MOS-transistor, the succession of layers consisting of said epitaxial layer, said first insulating layer and said first layer of electrically conductive material forming MOS-partial capacitances which are separated by the V-shaped trench and produce sub-zones of the opposite conductivity type to that of the epitaxial layer in the form of depletion zones in said epitaxial layer.
9. A semiconductor store as claimed in Claim 8, wherein said first layer of electrically conductive material consists of polycrvstalline silicon.
10. A semiconductor store as claimed in any one of the preceding Claims, wherein the word lines are made of aluminium.
11. A semiconductor store as claimed in any one of the preceding Claims, wherein the or each said insulating layer consists of silicon dioxide.
12. A semiconductor store substantially as herein before described with reference to and as illustrated in Figures 1 to 7, or Figures 8 to 10, or
Figures 11 and 12, or Figure 13, of the drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19792909820 DE2909820A1 (en) | 1979-03-13 | 1979-03-13 | SEMICONDUCTOR STORAGE WITH SINGLE TRANSISTOR CELLS IN V-MOS TECHNOLOGY |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2044997A true GB2044997A (en) | 1980-10-22 |
Family
ID=6065259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8008260A Withdrawn GB2044997A (en) | 1979-03-13 | 1980-03-11 | A semiconductor store comprising one-transistor storage cells formed by V-MOS Technology |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS55125668A (en) |
| DE (1) | DE2909820A1 (en) |
| FR (1) | FR2451615A1 (en) |
| GB (1) | GB2044997A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0118878A2 (en) * | 1983-03-07 | 1984-09-19 | Hitachi, Ltd. | Semiconductor memory device |
| EP0169332A2 (en) * | 1984-06-28 | 1986-01-29 | International Business Machines Corporation | High density one device memory |
| EP0175433A2 (en) * | 1984-09-11 | 1986-03-26 | Kabushiki Kaisha Toshiba | MOS dynamic RAM and manufacturing method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60257560A (en) * | 1984-06-04 | 1985-12-19 | Mitsubishi Electric Corp | Semiconductor memory device |
| US5204281A (en) * | 1990-09-04 | 1993-04-20 | Motorola, Inc. | Method of making dynamic random access memory cell having a trench capacitor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4003036A (en) * | 1975-10-23 | 1977-01-11 | American Micro-Systems, Inc. | Single IGFET memory cell with buried storage element |
| DE2703871C2 (en) * | 1977-01-31 | 1985-06-13 | Siemens AG, 1000 Berlin und 8000 München | Semiconductor memory with at least one V-MOS transistor |
| CA1118892A (en) * | 1977-12-27 | 1982-02-23 | John R. Edwards | Semiconductor device utilizing memory cells with sidewall charge storage regions |
-
1979
- 1979-03-13 DE DE19792909820 patent/DE2909820A1/en not_active Withdrawn
-
1980
- 1980-03-06 FR FR8005046A patent/FR2451615A1/en not_active Withdrawn
- 1980-03-11 GB GB8008260A patent/GB2044997A/en not_active Withdrawn
- 1980-03-11 JP JP3083880A patent/JPS55125668A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0118878A2 (en) * | 1983-03-07 | 1984-09-19 | Hitachi, Ltd. | Semiconductor memory device |
| EP0118878A3 (en) * | 1983-03-07 | 1988-01-13 | Hitachi, Ltd. | Semiconductor memory device |
| EP0169332A2 (en) * | 1984-06-28 | 1986-01-29 | International Business Machines Corporation | High density one device memory |
| EP0169332A3 (en) * | 1984-06-28 | 1989-09-06 | International Business Machines Corporation | High density one device memory |
| EP0175433A2 (en) * | 1984-09-11 | 1986-03-26 | Kabushiki Kaisha Toshiba | MOS dynamic RAM and manufacturing method thereof |
| EP0175433A3 (en) * | 1984-09-11 | 1986-12-30 | Kabushiki Kaisha Toshiba | Mos dynamic ram and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55125668A (en) | 1980-09-27 |
| FR2451615A1 (en) | 1980-10-10 |
| DE2909820A1 (en) | 1980-09-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |