FR2446012A1 - Cellule autoalignee a transistor mos avec incision en v pour memoire dynamique a acces selectif - Google Patents

Cellule autoalignee a transistor mos avec incision en v pour memoire dynamique a acces selectif

Info

Publication number
FR2446012A1
FR2446012A1 FR8000236A FR8000236A FR2446012A1 FR 2446012 A1 FR2446012 A1 FR 2446012A1 FR 8000236 A FR8000236 A FR 8000236A FR 8000236 A FR8000236 A FR 8000236A FR 2446012 A1 FR2446012 A1 FR 2446012A1
Authority
FR
France
Prior art keywords
incision
source
selective access
self
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR8000236A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
American Microsystems Holding Corp
Original Assignee
American Microsystems Holding Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Microsystems Holding Corp filed Critical American Microsystems Holding Corp
Publication of FR2446012A1 publication Critical patent/FR2446012A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

Chaque cellule 12 composant le réseau matriciel de la mémoire est constituée d'un élément unitaire de transistor à effet de champ et à grille isolée, formé dans une incision 22 en V située sur le côté d'un fil 16 de bits diffusé et directement au-dessus d'une région de source ensevelie 24. Les fils 16 de bits diffusés forment une région de source ou de drain tandis que la capacité de mémoire ensevelie 24 forme l'autre région de source et de drain. Du fait que le canal et la grille entre les deux régions de source et de drain sont situés sur une seule paroi latérale de l'incision 22, la capacitance grille-drain formée avec le fil 16 de bits est réduite et permet donc d'obtenir une puissance de signal accrue et un niveau de signal plus élevé. Applications notamment aux mémoires dynamiques à accès sélectif.
FR8000236A 1979-01-08 1980-01-07 Cellule autoalignee a transistor mos avec incision en v pour memoire dynamique a acces selectif Withdrawn FR2446012A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/001,712 US4214312A (en) 1979-01-08 1979-01-08 VMOS Field aligned dynamic ram cell

Publications (1)

Publication Number Publication Date
FR2446012A1 true FR2446012A1 (fr) 1980-08-01

Family

ID=21697449

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8000236A Withdrawn FR2446012A1 (fr) 1979-01-08 1980-01-07 Cellule autoalignee a transistor mos avec incision en v pour memoire dynamique a acces selectif

Country Status (8)

Country Link
US (1) US4214312A (fr)
JP (1) JPS5593253A (fr)
CA (1) CA1133135A (fr)
DE (1) DE3000120A1 (fr)
FR (1) FR2446012A1 (fr)
GB (1) GB2040565A (fr)
IT (1) IT7969474A0 (fr)
NL (1) NL7908313A (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4462040A (en) * 1979-05-07 1984-07-24 International Business Machines Corporation Single electrode U-MOSFET random access memory
US4369564A (en) * 1979-10-29 1983-01-25 American Microsystems, Inc. VMOS Memory cell and method for making same
JPS5834946B2 (ja) * 1980-10-16 1983-07-29 三菱電機株式会社 半導体記憶装置
JPS58106870A (ja) * 1981-12-18 1983-06-25 Nissan Motor Co Ltd パワ−ｍｏｓｆｅｔ
JPH0695566B2 (ja) * 1986-09-12 1994-11-24 日本電気株式会社 半導体メモリセル
FR2919112A1 (fr) * 2007-07-16 2009-01-23 St Microelectronics Crolles 2 Circuit integre comprenant un transistor et un condensateur et procede de fabrication
US9691898B2 (en) 2013-12-19 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Germanium profile for channel strain
US9287398B2 (en) 2014-02-14 2016-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor strain-inducing scheme

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4003036A (en) * 1975-10-23 1977-01-11 American Micro-Systems, Inc. Single IGFET memory cell with buried storage element

Also Published As

Publication number Publication date
US4214312A (en) 1980-07-22
DE3000120A1 (de) 1980-07-24
IT7969474A0 (it) 1979-12-24
GB2040565A (en) 1980-08-28
CA1133135A (fr) 1982-10-05
NL7908313A (nl) 1980-07-10
JPS5593253A (en) 1980-07-15

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Legal Events

Date Code Title Description
ST Notification of lapse