FR2395647A1 - Reseaux logiques programmables en combinaison et leur procede de fabrication - Google Patents

Reseaux logiques programmables en combinaison et leur procede de fabrication

Info

Publication number
FR2395647A1
FR2395647A1 FR7816944A FR7816944A FR2395647A1 FR 2395647 A1 FR2395647 A1 FR 2395647A1 FR 7816944 A FR7816944 A FR 7816944A FR 7816944 A FR7816944 A FR 7816944A FR 2395647 A1 FR2395647 A1 FR 2395647A1
Authority
FR
France
Prior art keywords
programmable logic
network
broadcasts
combination
manufacturing process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7816944A
Other languages
English (en)
Other versions
FR2395647B1 (fr
Inventor
Peruvemba S Balasubramanian
Claude R Bertin
Stephen B Greenspan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2395647A1 publication Critical patent/FR2395647A1/fr
Application granted granted Critical
Publication of FR2395647B1 publication Critical patent/FR2395647B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Abstract

Dispositif à réseaux logiques programmables. Le réseau ET et le réseau OU de ce dispositif sont combinés. Les lignes métalliques 6 d'entrée du réseau ET commandent les portes des dispositifs ET 22, transistors à effet de champ entre les diffusions 26 de masse et 24 de termes de produit. Celles-ci sont reliées par le contact 28 avec les lignes de produit 30 en silicium polycristallin du réseau OU, à un niveau différent qui commandent les dispositifs OU 32 entre les diffusions 26 de masse et les diffusions 34 de sortie. Ceci permet d'augmenter la densité des réseaux. Peut être utilisé dans tout dispositif à réseaux logiques programmables pour réaliser un ensemble de fonctions logiques.
FR7816944A 1977-06-24 1978-05-29 Reseaux logiques programmables en combinaison et leur procede de fabrication Granted FR2395647A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/809,877 US4140967A (en) 1977-06-24 1977-06-24 Merged array PLA device, circuit, fabrication method and testing technique

Publications (2)

Publication Number Publication Date
FR2395647A1 true FR2395647A1 (fr) 1979-01-19
FR2395647B1 FR2395647B1 (fr) 1982-09-17

Family

ID=25202402

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7816944A Granted FR2395647A1 (fr) 1977-06-24 1978-05-29 Reseaux logiques programmables en combinaison et leur procede de fabrication

Country Status (5)

Country Link
US (1) US4140967A (fr)
JP (1) JPS5434688A (fr)
DE (1) DE2826722A1 (fr)
FR (1) FR2395647A1 (fr)
GB (1) GB1596337A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0005847A1 (fr) * 1978-06-05 1979-12-12 International Business Machines Corporation Circuit de mémoire et son utilisation dans un réseau logique programmable électriquement
EP0095418A1 (fr) * 1982-05-25 1983-11-30 Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux - E.F.C.I.S. Circuit intégré logique conçu de manière à simplifier son implantation sur un substrat

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4220917A (en) * 1978-07-31 1980-09-02 International Business Machines Corporation Test circuitry for module interconnection network
US4241307A (en) * 1978-08-18 1980-12-23 International Business Machines Corporation Module interconnection testing scheme
DE2951946A1 (de) * 1979-12-22 1981-07-02 Ibm Deutschland Gmbh, 7000 Stuttgart Fehlererkennungs- und -korrektureinrichtung fuer eine logische anordnung
DE3114679A1 (de) * 1980-04-11 1982-01-14 Hitachi, Ltd., Tokyo Integrierte schaltung mit mehrschichtenverbindungen
DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
US4395646A (en) * 1980-11-03 1983-07-26 International Business Machines Corp. Logic performing cell for use in array structures
US4377849A (en) * 1980-12-29 1983-03-22 International Business Machines Corporation Macro assembler process for automated circuit design
US4404635A (en) * 1981-03-27 1983-09-13 International Business Machines Corporation Programmable integrated circuit and method of testing the circuit before it is programmed
GB2097581A (en) * 1981-04-24 1982-11-03 Hitachi Ltd Shielding semiconductor integrated circuit devices from light
US4467439A (en) * 1981-06-30 1984-08-21 Ibm Corporation OR Product term function in the search array of a PLA
US4441075A (en) * 1981-07-02 1984-04-03 International Business Machines Corporation Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection
US4461000A (en) * 1982-03-01 1984-07-17 Harris Corporation ROM/PLA Structure and method of testing
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US4506341A (en) * 1982-06-10 1985-03-19 International Business Machines Corporation Interlaced programmable logic array having shared elements
US4566022A (en) * 1983-01-27 1986-01-21 International Business Machines Corporation Flexible/compressed array macro design
JPH07119789B2 (ja) * 1983-02-04 1995-12-20 株式会社日立製作所 半導体集積回路装置及びその診断方法
JPS59172761A (ja) * 1983-03-23 1984-09-29 Hitachi Ltd 半導体装置
JPH073862B2 (ja) * 1983-07-27 1995-01-18 株式会社日立製作所 半導体記憶装置
KR940002772B1 (ko) * 1984-08-31 1994-04-02 가부시기가이샤 히다찌세이사꾸쇼 반도체 집적회로 장치 및 그 제조방법
EP0196083B1 (fr) * 1985-03-26 1992-07-22 Kabushiki Kaisha Toshiba Circuit logique
US4684884A (en) * 1985-07-02 1987-08-04 Gte Communication Systems Corporation Universal test circuit for integrated circuit packages
DE3611557A1 (de) * 1986-04-07 1987-10-29 Nixdorf Computer Ag In integrierter technik hergestellter logik-array-baustein zur erstellung integrierter schaltungen
JP2703373B2 (ja) * 1989-12-01 1998-01-26 シャープ株式会社 板状体の把持装置
GB9007492D0 (en) * 1990-04-03 1990-05-30 Pilkington Micro Electronics Semiconductor integrated circuit
US5430734A (en) * 1993-02-12 1995-07-04 Metalithic Systems, Inc. Fault-tolerant waferscale integrated circuit device and method
US5732246A (en) * 1995-06-07 1998-03-24 International Business Machines Corporation Programmable array interconnect latch
US5651013A (en) * 1995-11-14 1997-07-22 International Business Machines Corporation Programmable circuits for test and operation of programmable gate arrays
US5781031A (en) * 1995-11-21 1998-07-14 International Business Machines Corporation Programmable logic array
US5684413A (en) * 1996-03-28 1997-11-04 Philips Electronics North America Corp. Condensed single block PLA plus PAL architecture
US6426650B1 (en) 1999-12-28 2002-07-30 Koninklijke Philips Electronics, N.V. Integrated circuit with metal programmable logic having enhanced reliability

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3936812A (en) * 1974-12-30 1976-02-03 Ibm Corporation Segmented parallel rail paths for input/output signals

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3790885A (en) * 1972-03-27 1974-02-05 Ibm Serial test patterns for mosfet testing
US3789205A (en) * 1972-09-28 1974-01-29 Ibm Method of testing mosfet planar boards
GB1468346A (en) * 1973-02-28 1977-03-23 Mullard Ltd Devices having conductive tracks at different levels with interconnections therebetween

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3936812A (en) * 1974-12-30 1976-02-03 Ibm Corporation Segmented parallel rail paths for input/output signals

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/76 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0005847A1 (fr) * 1978-06-05 1979-12-12 International Business Machines Corporation Circuit de mémoire et son utilisation dans un réseau logique programmable électriquement
EP0095418A1 (fr) * 1982-05-25 1983-11-30 Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux - E.F.C.I.S. Circuit intégré logique conçu de manière à simplifier son implantation sur un substrat
FR2527868A1 (fr) * 1982-05-25 1983-12-02 Efcis Circuit integre logique concu de maniere a simplifier son implantation sur un substrat

Also Published As

Publication number Publication date
US4140967A (en) 1979-02-20
DE2826722A1 (de) 1979-01-18
FR2395647B1 (fr) 1982-09-17
JPS6360535B2 (fr) 1988-11-24
JPS5434688A (en) 1979-03-14
GB1596337A (en) 1981-08-26

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