FR2396470A1 - Circuit logique a transistors a effet de champ travaillant en mode d'appauvrissement/enrichissement - Google Patents

Circuit logique a transistors a effet de champ travaillant en mode d'appauvrissement/enrichissement

Info

Publication number
FR2396470A1
FR2396470A1 FR7818482A FR7818482A FR2396470A1 FR 2396470 A1 FR2396470 A1 FR 2396470A1 FR 7818482 A FR7818482 A FR 7818482A FR 7818482 A FR7818482 A FR 7818482A FR 2396470 A1 FR2396470 A1 FR 2396470A1
Authority
FR
France
Prior art keywords
depletion
logic circuit
effect transistor
field
transistor logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7818482A
Other languages
English (en)
Other versions
FR2396470B1 (fr
Inventor
Eugene M Blaser
Donald A Conrad
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2396470A1 publication Critical patent/FR2396470A1/fr
Application granted granted Critical
Publication of FR2396470B1 publication Critical patent/FR2396470B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

Circuit logique à transistors à effet de champ travaillant en mode d'appauvrissement/enrichissement. Le transistor d'entrée T1, connecté entre le noeud d'entrée A et le noeud X, a sa porte à la masse. Le transistor T2 est un dispositif, travaillant en mode d'appauvrissement, auto-polarisé connecté entre + 5V et X. Un transistor T3 a sa porte connectée à X, sa source à la masse et son drain fournissant une sortie. Des circuits logiques peuvent être réalisés en multipliant les transistors T3 reliés à des sorties différentes ou en multipliant les branches T1, T2, T3, les drains des transistors de sortie T3 (tels que T3 et T13) étant mis en commun. Peut être utilisé pour réaliser tout type de circuit logique.
FR7818482A 1977-06-30 1978-06-13 Circuit logique a transistors a effet de champ travaillant en mode d'appauvrissement/enrichissement Granted FR2396470A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/811,737 US4110633A (en) 1977-06-30 1977-06-30 Depletion/enhancement mode FET logic circuit

Publications (2)

Publication Number Publication Date
FR2396470A1 true FR2396470A1 (fr) 1979-01-26
FR2396470B1 FR2396470B1 (fr) 1982-06-04

Family

ID=25207423

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7818482A Granted FR2396470A1 (fr) 1977-06-30 1978-06-13 Circuit logique a transistors a effet de champ travaillant en mode d'appauvrissement/enrichissement

Country Status (5)

Country Link
US (1) US4110633A (fr)
JP (1) JPS5412665A (fr)
DE (1) DE2825443C2 (fr)
FR (1) FR2396470A1 (fr)
GB (1) GB1570666A (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295064A (en) * 1978-06-30 1981-10-13 International Business Machines Corporation Logic and array logic driving circuits
JPS55115721A (en) * 1979-02-28 1980-09-05 Nec Corp Integrated circuit device
US4307308A (en) * 1979-11-19 1981-12-22 Gte Laboratories Incorporated Digital signal conversion circuit
JPS5769335U (fr) * 1980-10-14 1982-04-26
US4463273A (en) * 1981-10-26 1984-07-31 Rca Corporation Electronic circuits and structures employing enhancement and depletion type IGFETs
US4490632A (en) * 1981-11-23 1984-12-25 Texas Instruments Incorporated Noninverting amplifier circuit for one propagation delay complex logic gates
JPS5999296A (ja) * 1982-11-29 1984-06-07 株式会社日立製作所 沸騰水型重水炉の工学的安全施設
JPS60500437A (ja) * 1983-02-04 1985-03-28 モトロ−ラ・インコ−ポレ−テツド 短絡保護バツフア回路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623132A (en) * 1970-12-14 1971-11-23 North American Rockwell Charge sensing circuit
US3775693A (en) * 1971-11-29 1973-11-27 Moskek Co Mosfet logic inverter for integrated circuits
US3866186A (en) * 1972-05-16 1975-02-11 Tokyo Shibaura Electric Co Logic circuit arrangement employing insulated gate field effect transistors
US3832574A (en) * 1972-12-29 1974-08-27 Ibm Fast insulated gate field effect transistor circuit using multiple threshold technology
JPS5160440A (en) * 1974-11-22 1976-05-26 Hitachi Ltd Kotaiatsuyo mis fet suitsuchingukairo

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
EXBK/72 *
EXBK/75 *
EXBK/76 *

Also Published As

Publication number Publication date
FR2396470B1 (fr) 1982-06-04
DE2825443C2 (de) 1983-06-09
US4110633A (en) 1978-08-29
GB1570666A (en) 1980-07-02
JPS5648095B2 (fr) 1981-11-13
JPS5412665A (en) 1979-01-30
DE2825443A1 (de) 1979-01-11

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Legal Events

Date Code Title Description
ST Notification of lapse