JPS5412665A - Logic circuit having input fet - Google Patents

Logic circuit having input fet

Info

Publication number
JPS5412665A
JPS5412665A JP5902978A JP5902978A JPS5412665A JP S5412665 A JPS5412665 A JP S5412665A JP 5902978 A JP5902978 A JP 5902978A JP 5902978 A JP5902978 A JP 5902978A JP S5412665 A JPS5412665 A JP S5412665A
Authority
JP
Japan
Prior art keywords
logic circuit
input fet
fet
input
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5902978A
Other languages
English (en)
Other versions
JPS5648095B2 (ja
Inventor
Emu Burezaa Yuujin
Ee Konratsudo Donarudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5412665A publication Critical patent/JPS5412665A/ja
Publication of JPS5648095B2 publication Critical patent/JPS5648095B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
JP5902978A 1977-06-30 1978-05-19 Logic circuit having input fet Granted JPS5412665A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/811,737 US4110633A (en) 1977-06-30 1977-06-30 Depletion/enhancement mode FET logic circuit

Publications (2)

Publication Number Publication Date
JPS5412665A true JPS5412665A (en) 1979-01-30
JPS5648095B2 JPS5648095B2 (ja) 1981-11-13

Family

ID=25207423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5902978A Granted JPS5412665A (en) 1977-06-30 1978-05-19 Logic circuit having input fet

Country Status (5)

Country Link
US (1) US4110633A (ja)
JP (1) JPS5412665A (ja)
DE (1) DE2825443C2 (ja)
FR (1) FR2396470A1 (ja)
GB (1) GB1570666A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55115721A (en) * 1979-02-28 1980-09-05 Nec Corp Integrated circuit device

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295064A (en) * 1978-06-30 1981-10-13 International Business Machines Corporation Logic and array logic driving circuits
US4307308A (en) * 1979-11-19 1981-12-22 Gte Laboratories Incorporated Digital signal conversion circuit
JPS5769335U (ja) * 1980-10-14 1982-04-26
US4463273A (en) * 1981-10-26 1984-07-31 Rca Corporation Electronic circuits and structures employing enhancement and depletion type IGFETs
US4490632A (en) * 1981-11-23 1984-12-25 Texas Instruments Incorporated Noninverting amplifier circuit for one propagation delay complex logic gates
JPS5999296A (ja) * 1982-11-29 1984-06-07 株式会社日立製作所 沸騰水型重水炉の工学的安全施設
EP0141819A4 (en) * 1983-02-04 1986-06-05 Motorola Inc BUFFER CIRCUIT PROTECTED AGAINST SHORT CIRCUITS.

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623132A (en) * 1970-12-14 1971-11-23 North American Rockwell Charge sensing circuit
US3775693A (en) * 1971-11-29 1973-11-27 Moskek Co Mosfet logic inverter for integrated circuits
US3866186A (en) * 1972-05-16 1975-02-11 Tokyo Shibaura Electric Co Logic circuit arrangement employing insulated gate field effect transistors
US3832574A (en) * 1972-12-29 1974-08-27 Ibm Fast insulated gate field effect transistor circuit using multiple threshold technology
JPS5160440A (en) * 1974-11-22 1976-05-26 Hitachi Ltd Kotaiatsuyo mis fet suitsuchingukairo

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55115721A (en) * 1979-02-28 1980-09-05 Nec Corp Integrated circuit device
JPS6222488B2 (ja) * 1979-02-28 1987-05-18 Nippon Electric Co

Also Published As

Publication number Publication date
JPS5648095B2 (ja) 1981-11-13
US4110633A (en) 1978-08-29
DE2825443A1 (de) 1979-01-11
FR2396470A1 (fr) 1979-01-26
FR2396470B1 (ja) 1982-06-04
DE2825443C2 (de) 1983-06-09
GB1570666A (en) 1980-07-02

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