FR2421423B1 - Dispositif de commande de branchement dans un systeme de traitement de donnees - Google Patents

Dispositif de commande de branchement dans un systeme de traitement de donnees

Info

Publication number
FR2421423B1
FR2421423B1 FR7905119A FR7905119A FR2421423B1 FR 2421423 B1 FR2421423 B1 FR 2421423B1 FR 7905119 A FR7905119 A FR 7905119A FR 7905119 A FR7905119 A FR 7905119A FR 2421423 B1 FR2421423 B1 FR 2421423B1
Authority
FR
France
Prior art keywords
control device
data processing
processing system
connection control
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7905119A
Other languages
English (en)
Other versions
FR2421423A1 (fr
Inventor
Richard G Forster
John K Howard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2421423A1 publication Critical patent/FR2421423A1/fr
Application granted granted Critical
Publication of FR2421423B1 publication Critical patent/FR2421423B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
FR7905119A 1978-03-31 1979-02-22 Dispositif de commande de branchement dans un systeme de traitement de donnees Expired FR2421423B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/892,243 US4181942A (en) 1978-03-31 1978-03-31 Program branching method and apparatus

Publications (2)

Publication Number Publication Date
FR2421423A1 FR2421423A1 (fr) 1979-10-26
FR2421423B1 true FR2421423B1 (fr) 1987-04-24

Family

ID=25399625

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7905119A Expired FR2421423B1 (fr) 1978-03-31 1979-02-22 Dispositif de commande de branchement dans un systeme de traitement de donnees

Country Status (7)

Country Link
US (1) US4181942A (fr)
JP (1) JPS54131843A (fr)
BR (1) BR7901934A (fr)
DE (1) DE2910839A1 (fr)
FR (1) FR2421423B1 (fr)
GB (1) GB2017984B (fr)
IT (1) IT1166705B (fr)

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US4309753A (en) * 1979-01-03 1982-01-05 Honeywell Information System Inc. Apparatus and method for next address generation in a data processing system
JPS6064235A (ja) * 1983-09-20 1985-04-12 Toshiba Corp Ｃｔスキヤナ
JPS61229134A (ja) * 1985-04-03 1986-10-13 Nec Corp マイクロコンピユ−タ
JPS6341932A (ja) * 1985-08-22 1988-02-23 Nec Corp 分岐命令処理装置
JPS63197232A (ja) * 1987-02-12 1988-08-16 Toshiba Corp マイクロプロセツサ
JP3452655B2 (ja) * 1993-09-27 2003-09-29 株式会社日立製作所 ディジタル信号処理プロセッサおよびそれを用いて命令を実行する方法
US6732253B1 (en) 2000-11-13 2004-05-04 Chipwrights Design, Inc. Loop handling for single instruction multiple datapath processor architectures
US6931518B1 (en) 2000-11-28 2005-08-16 Chipwrights Design, Inc. Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic
US7165169B2 (en) * 2001-05-04 2007-01-16 Ip-First, Llc Speculative branch target address cache with selective override by secondary predictor based on branch instruction type
US7200740B2 (en) * 2001-05-04 2007-04-03 Ip-First, Llc Apparatus and method for speculatively performing a return instruction in a microprocessor
US20020194461A1 (en) * 2001-05-04 2002-12-19 Ip First Llc Speculative branch target address cache
US7707397B2 (en) * 2001-05-04 2010-04-27 Via Technologies, Inc. Variable group associativity branch target address cache delivering multiple target addresses per cache line
US7165168B2 (en) * 2003-01-14 2007-01-16 Ip-First, Llc Microprocessor with branch target address cache update queue
US6895498B2 (en) * 2001-05-04 2005-05-17 Ip-First, Llc Apparatus and method for target address replacement in speculative branch target address cache
US7134005B2 (en) * 2001-05-04 2006-11-07 Ip-First, Llc Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte
US6886093B2 (en) * 2001-05-04 2005-04-26 Ip-First, Llc Speculative hybrid branch direction predictor
US7203824B2 (en) * 2001-07-03 2007-04-10 Ip-First, Llc Apparatus and method for handling BTAC branches that wrap across instruction cache lines
US6823444B1 (en) * 2001-07-03 2004-11-23 Ip-First, Llc Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrap
US7234045B2 (en) * 2001-07-03 2007-06-19 Ip-First, Llc Apparatus and method for handling BTAC branches that wrap across instruction cache lines
US7162619B2 (en) * 2001-07-03 2007-01-09 Ip-First, Llc Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer
US7159097B2 (en) * 2002-04-26 2007-01-02 Ip-First, Llc Apparatus and method for buffering instructions and late-generated related information using history of previous load/shifts
US6970985B2 (en) 2002-07-09 2005-11-29 Bluerisc Inc. Statically speculative memory accessing
US7185186B2 (en) 2003-01-14 2007-02-27 Ip-First, Llc Apparatus and method for resolving deadlock fetch conditions involving branch target address cache
US7143269B2 (en) * 2003-01-14 2006-11-28 Ip-First, Llc Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessor
US7152154B2 (en) * 2003-01-16 2006-12-19 Ip-First, Llc. Apparatus and method for invalidation of redundant branch target address cache entries
US7178010B2 (en) * 2003-01-16 2007-02-13 Ip-First, Llc Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack
US7237098B2 (en) * 2003-09-08 2007-06-26 Ip-First, Llc Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
US20050114850A1 (en) * 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US7996671B2 (en) * 2003-11-17 2011-08-09 Bluerisc Inc. Security of program executables and microprocessors based on compiler-architecture interaction
US8607209B2 (en) 2004-02-04 2013-12-10 Bluerisc Inc. Energy-focused compiler-assisted branch prediction
US20070294181A1 (en) * 2006-05-22 2007-12-20 Saurabh Chheda Flexible digital rights management with secure snippets
US20080126766A1 (en) 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering
US20080154379A1 (en) * 2006-12-22 2008-06-26 Musculoskeletal Transplant Foundation Interbody fusion hybrid graft
EP2120244A1 (fr) 2008-05-15 2009-11-18 ABB Technology AG Disjoncteur haute pression

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US3239820A (en) * 1962-02-16 1966-03-08 Burroughs Corp Digital computer with automatic repeating of program segments
US3292153A (en) * 1962-10-01 1966-12-13 Burroughs Corp Memory system
US3292155A (en) * 1963-03-15 1966-12-13 Burroughs Corp Computer branch command
US3297998A (en) * 1963-06-10 1967-01-10 Beckman Instruments Inc List control
US3366929A (en) * 1964-12-30 1968-01-30 Ibm Computing system embodying flexible subroutine capabilities
FR1536616A (fr) * 1966-09-21 Ibm Système de traitement d'instructions avec des perfectionnements pour le branchementet les boucles du programme
GB1506840A (en) * 1967-09-12 1978-04-12 Licentia Gmbh Method of advancing the point of impact for passive-location missiles guided by means of proportional navigation in the self-guide phase
DE1578299B2 (de) * 1967-10-14 1976-03-11 Licenti a Patent-Verwaltung s-GmbH, 6000 Frankfurt Verfahren zur treffpunktvorverlegung fuer passiv ortende in der eigenlenkphase mittels proportionalnavigation gelenkte geschosse
US3577190A (en) * 1968-06-26 1971-05-04 Ibm Apparatus in a digital computer for allowing the skipping of predetermined instructions in a sequence of instructions, in response to the occurrence of certain conditions
US3573853A (en) * 1968-12-04 1971-04-06 Texas Instruments Inc Look-ahead control for operation of program loops
US3577189A (en) * 1969-01-15 1971-05-04 Ibm Apparatus and method in a digital computer for allowing improved program branching with branch anticipation reduction of the number of branches, and reduction of branch delays
US3665402A (en) * 1970-02-16 1972-05-23 Sanders Associates Inc Computer addressing apparatus
FR2226066A5 (fr) * 1970-10-13 1974-11-08 Bodenseewerk Geraetetech
US3737867A (en) * 1971-02-12 1973-06-05 D Cavin Digital computer with accumulator sign bit indexing
US3713108A (en) * 1971-03-25 1973-01-23 Ibm Branch control for a digital machine
US3728686A (en) * 1971-06-07 1973-04-17 Rca Corp Computer memory with improved next word accessing
US3728689A (en) * 1971-06-21 1973-04-17 Sanders Associates Inc Program branching and register addressing procedures and apparatus
US3793631A (en) * 1972-09-22 1974-02-19 Westinghouse Electric Corp Digital computer apparatus operative with jump instructions
JPS5324151B2 (fr) * 1972-12-25 1978-07-19
IT1000638B (it) * 1973-12-28 1976-04-10 Olivetti & Co Spa Calcolatore elettronico con dispo sitivo di deviazione dei micropro grammi
US3958227A (en) * 1974-09-24 1976-05-18 International Business Machines Corporation Control store system with flexible control word selection

Also Published As

Publication number Publication date
US4181942A (en) 1980-01-01
BR7901934A (pt) 1979-10-23
FR2421423A1 (fr) 1979-10-26
JPS54131843A (en) 1979-10-13
JPS5732814B2 (fr) 1982-07-13
GB2017984A (en) 1979-10-10
GB2017984B (en) 1982-05-12
DE2910839A1 (de) 1979-10-04
IT7921036A0 (it) 1979-03-16
IT1166705B (it) 1987-05-06

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Legal Events

Date Code Title Description
ST Notification of lapse