FR2472233B1 - Dispositif de commande de memoire pour systeme de traitement des donnees - Google Patents

Dispositif de commande de memoire pour systeme de traitement des donnees

Info

Publication number
FR2472233B1
FR2472233B1 FR808026475A FR8026475A FR2472233B1 FR 2472233 B1 FR2472233 B1 FR 2472233B1 FR 808026475 A FR808026475 A FR 808026475A FR 8026475 A FR8026475 A FR 8026475A FR 2472233 B1 FR2472233 B1 FR 2472233B1
Authority
FR
France
Prior art keywords
control device
data processing
processing system
memory control
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR808026475A
Other languages
English (en)
Other versions
FR2472233A1 (fr
Inventor
Masato Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Publication of FR2472233A1 publication Critical patent/FR2472233A1/fr
Application granted granted Critical
Publication of FR2472233B1 publication Critical patent/FR2472233B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
FR808026475A 1979-12-14 1980-12-12 Dispositif de commande de memoire pour systeme de traitement des donnees Expired FR2472233B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16326079A JPS5687282A (en) 1979-12-14 1979-12-14 Data processor

Publications (2)

Publication Number Publication Date
FR2472233A1 FR2472233A1 (fr) 1981-06-26
FR2472233B1 true FR2472233B1 (fr) 1989-06-30

Family

ID=15770413

Family Applications (1)

Application Number Title Priority Date Filing Date
FR808026475A Expired FR2472233B1 (fr) 1979-12-14 1980-12-12 Dispositif de commande de memoire pour systeme de traitement des donnees

Country Status (3)

Country Link
US (3) US4502110A (fr)
JP (1) JPS5687282A (fr)
FR (1) FR2472233B1 (fr)

Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687282A (en) * 1979-12-14 1981-07-15 Nec Corp Data processor
JPS5853075A (ja) * 1981-09-25 1983-03-29 Nec Corp 高速分離バツフアを備えた情報処理装置
JPS58102381A (ja) * 1981-12-15 1983-06-17 Nec Corp バツフアメモリ
JPS5948879A (ja) * 1982-09-10 1984-03-21 Hitachi Ltd 記憶制御方式
WO1984002799A1 (fr) * 1982-12-30 1984-07-19 Ibm Systeme de memoire hierarchique comprenant des antememoires pour stocker des donnees et des instructions
US4737933A (en) * 1983-02-22 1988-04-12 Storage Technology Partners CMOS multiport general purpose register
JPS60123936A (ja) * 1983-12-07 1985-07-02 Fujitsu Ltd バッフア記憶制御方式
DE3379498D1 (en) * 1983-12-27 1989-05-03 Ford Motor Co Apparatus for periodically oxidizing particulates collected from exhaust gases
JPH0652511B2 (ja) * 1984-12-14 1994-07-06 株式会社日立製作所 情報処理装置のアドレス変換方式
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
JP2539357B2 (ja) * 1985-03-15 1996-10-02 株式会社日立製作所 デ−タ処理装置
US4774653A (en) * 1985-08-07 1988-09-27 Hewlett-Packard Company Hybrid hardware/software method and apparatus for virtual memory address translation using primary and secondary translation buffers
US4722047A (en) * 1985-08-29 1988-01-26 Ncr Corporation Prefetch circuit and associated method for operation with a virtual command emulator
US5349672A (en) * 1986-03-17 1994-09-20 Hitachi, Ltd. Data processor having logical address memories and purge capabilities
JPS62222344A (ja) * 1986-03-25 1987-09-30 Hitachi Ltd アドレス変換機構
JPS6324428A (ja) * 1986-07-17 1988-02-01 Mitsubishi Electric Corp キヤツシユメモリ
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US4888689A (en) * 1986-10-17 1989-12-19 Amdahl Corporation Apparatus and method for improving cache access throughput in pipelined processors
US5095424A (en) * 1986-10-17 1992-03-10 Amdahl Corporation Computer system architecture implementing split instruction and operand cache line-pair-state management
US4811215A (en) * 1986-12-12 1989-03-07 Intergraph Corporation Instruction execution accelerator for a pipelined digital machine with virtual memory
US5155833A (en) * 1987-05-11 1992-10-13 At&T Bell Laboratories Multi-purpose cache memory selectively addressable either as a boot memory or as a cache memory
US5168560A (en) * 1987-05-29 1992-12-01 Amdahl Corporation Microprocessor system private split cache tag stores with the system tag store having a different validity bit for the same data line
US5249276A (en) * 1987-06-22 1993-09-28 Hitachi, Ltd. Address translation apparatus having a memory access privilege check capability data which uses mask data to select bit positions of priviledge
US5167023A (en) * 1988-02-01 1992-11-24 International Business Machines Translating a dynamic transfer control instruction address in a simulated CPU processor
US5214770A (en) * 1988-04-01 1993-05-25 Digital Equipment Corporation System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command
US5513332A (en) * 1988-05-31 1996-04-30 Extended Systems, Inc. Database management coprocessor for on-the-fly providing data from disk media to all without first storing data in memory therebetween
GB8817911D0 (en) * 1988-07-27 1988-09-01 Int Computers Ltd Data processing apparatus
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5029070A (en) * 1988-08-25 1991-07-02 Edge Computer Corporation Coherent cache structures and methods
US5027270A (en) * 1988-10-11 1991-06-25 Mips Computer Systems, Inc. Processor controlled interface with instruction streaming
US4905141A (en) * 1988-10-25 1990-02-27 International Business Machines Corporation Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification
US6092153A (en) * 1988-11-14 2000-07-18 Lass; Stanley Edwin Subsettable top level cache
US5201041A (en) * 1988-12-29 1993-04-06 International Business Machines Corporation Cache bypass apparatus
US5155816A (en) * 1989-02-10 1992-10-13 Intel Corporation Pipelined apparatus and method for controlled loading of floating point data in a microprocessor
JPH0760411B2 (ja) * 1989-05-23 1995-06-28 株式会社日立製作所 バッファ記憶制御装置
US5623650A (en) * 1989-12-29 1997-04-22 Cray Research, Inc. Method of processing a sequence of conditional vector IF statements
US5197130A (en) * 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
US5598547A (en) * 1990-06-11 1997-01-28 Cray Research, Inc. Vector processor having functional unit paths of differing pipeline lengths
US5404482A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills
US5404483A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
FR2664719A1 (fr) * 1990-07-10 1992-01-17 Philips Electronique Lab Dispositif de controle pour une memoire tampon a partitionnement reconfigurable.
JP2646854B2 (ja) * 1990-12-18 1997-08-27 三菱電機株式会社 マイクロプロセッサ
US5454093A (en) * 1991-02-25 1995-09-26 International Business Machines Corporation Buffer bypass for quick data access
JP2514292B2 (ja) * 1991-04-25 1996-07-10 インターナショナル・ビジネス・マシーンズ・コーポレイション オペランドペ―ジメモリ及び命令ペ―ジメモリを有するコンピュ―タシステム
US5341485A (en) * 1991-05-07 1994-08-23 International Business Machines Corporation Multiple virtual address translation per computer cycle
US5423014A (en) * 1991-10-29 1995-06-06 Intel Corporation Instruction fetch unit with early instruction fetch mechanism
US5638537A (en) * 1993-01-29 1997-06-10 Mitsubishi Denki Kabushiki Kaisha Cache system with access mode determination for prioritizing accesses to cache memory
DE4410060B4 (de) * 1993-04-08 2006-02-09 Hewlett-Packard Development Co., L.P., Houston Übersetzungsvorrichtung zum Umsetzen einer virtuellen Speicheradresse in eine physikalische Speicheradresse
US5860127A (en) 1995-06-01 1999-01-12 Hitachi, Ltd. Cache memory employing dynamically controlled data array start timing and a microcomputer using the same
EP0752645B1 (fr) * 1995-07-07 2017-11-22 Oracle America, Inc. Commande accordable par logiciel d'antémémoire d'une architecture "Harvard", en utilisant des instructions de pré-extraction
US5790823A (en) * 1995-07-13 1998-08-04 International Business Machines Corporation Operand prefetch table
US5761468A (en) * 1996-05-15 1998-06-02 Sun Microsystems Inc Hardware mechanism for optimizing instruction and data prefetching by forming augmented prefetch instructions
US5893930A (en) * 1996-07-12 1999-04-13 International Business Machines Corporation Predictive translation of a data address utilizing sets of associative entries stored consecutively in a translation lookaside buffer
US6189074B1 (en) 1997-03-19 2001-02-13 Advanced Micro Devices, Inc. Mechanism for storing system level attributes in a translation lookaside buffer
US6446189B1 (en) 1999-06-01 2002-09-03 Advanced Micro Devices, Inc. Computer system including a novel address translation mechanism
US6510508B1 (en) 2000-06-15 2003-01-21 Advanced Micro Devices, Inc. Translation lookaside buffer flush filter
US6665788B1 (en) 2001-07-13 2003-12-16 Advanced Micro Devices, Inc. Reducing latency for a relocation cache lookup and address mapping in a distributed memory system
US9514055B2 (en) * 2009-12-31 2016-12-06 Seagate Technology Llc Distributed media cache for data storage systems
US8639882B2 (en) * 2011-12-14 2014-01-28 Nvidia Corporation Methods and apparatus for source operand collector caching
US9311239B2 (en) 2013-03-14 2016-04-12 Intel Corporation Power efficient level one data cache access with pre-validated tags
US11288199B2 (en) 2019-02-28 2022-03-29 Micron Technology, Inc. Separate read-only cache and write-read cache in a memory sub-system
US10908821B2 (en) * 2019-02-28 2021-02-02 Micron Technology, Inc. Use of outstanding command queues for separate read-only cache and write-read cache in a memory sub-system
CN112347011B (zh) * 2020-11-11 2024-04-05 歌尔科技有限公司 双机通信方法、终端设备及存储介质
US11853231B2 (en) 2021-06-24 2023-12-26 Ati Technologies Ulc Transmission of address translation type packets

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1218761B (de) * 1963-07-19 1966-06-08 International Business Machines Corporation, Armonk, N. Y. (V. St. A.) Datenspeidbereinrichtung
US3470540A (en) * 1967-04-24 1969-09-30 Rca Corp Multiprocessing computer system with special instruction sequencing
US3618041A (en) * 1968-10-31 1971-11-02 Hitachi Ltd Memory control system
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
US3699533A (en) * 1970-10-29 1972-10-17 Rca Corp Memory system including buffer memories
DE2120410A1 (de) * 1971-04-26 1972-11-02 Siemens AG, 1000 Berlin u. 8000 München Datenverarbeitungsanlage mit einem in Teilspeicher unterteilten Arbeitsspeicher
US3761881A (en) * 1971-06-30 1973-09-25 Ibm Translation storage scheme for virtual memory system
GB1354827A (en) * 1971-08-25 1974-06-05 Ibm Data processing systems
US4010451A (en) * 1972-10-03 1977-03-01 National Research Development Corporation Data structure processor
US3928857A (en) * 1973-08-30 1975-12-23 Ibm Instruction fetch apparatus with combined look-ahead and look-behind capability
FR130806A (fr) * 1973-11-21
US3947823A (en) * 1973-12-26 1976-03-30 International Business Machines Corp. Means for coordinating asynchronous main store accesses in a multiprocessing system using virtual storage
US3938097A (en) * 1974-04-01 1976-02-10 Xerox Corporation Memory and buffer arrangement for digital computers
US3906458A (en) * 1974-08-28 1975-09-16 Burroughs Corp Odd-sized memory having a plurality of even-sized storage elements of the same capacity
DE2547488C2 (de) * 1975-10-23 1982-04-15 Ibm Deutschland Gmbh, 7000 Stuttgart Mikroprogrammierte Datenverarbeitungsanlage
US4323968A (en) * 1978-10-26 1982-04-06 International Business Machines Corporation Multilevel storage system having unitary control of data transfers
JPS5576447A (en) * 1978-12-01 1980-06-09 Fujitsu Ltd Address control system for software simulation
US4312036A (en) * 1978-12-11 1982-01-19 Honeywell Information Systems Inc. Instruction buffer apparatus of a cache unit
US4298929A (en) * 1979-01-26 1981-11-03 International Business Machines Corporation Integrated multilevel storage hierarchy for a data processing system with improved channel to memory write capability
US4527237A (en) * 1979-10-11 1985-07-02 Nanodata Computer Corporation Data processing system
DE2948159C2 (de) * 1979-11-29 1983-10-27 Siemens AG, 1000 Berlin und 8000 München Integrierter Speicherbaustein mit wählbaren Betriebsfunktionen
JPS5687282A (en) * 1979-12-14 1981-07-15 Nec Corp Data processor
US4315312A (en) * 1979-12-19 1982-02-09 Ncr Corporation Cache memory having a variable data block size
US4355355A (en) * 1980-03-19 1982-10-19 International Business Machines Corp. Address generating mechanism for multiple virtual spaces
US4506325A (en) * 1980-03-24 1985-03-19 Sperry Corporation Reflexive utilization of descriptors to reconstitute computer instructions which are Huffman-like encoded
US4500952A (en) * 1980-05-23 1985-02-19 International Business Machines Corporation Mechanism for control of address translation by a program using a plurality of translation tables
US4370710A (en) * 1980-08-26 1983-01-25 Control Data Corporation Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses
US4386402A (en) * 1980-09-25 1983-05-31 Bell Telephone Laboratories, Incorporated Computer with dual vat buffers for accessing a common memory shared by a cache and a processor interrupt stack
US4437149A (en) * 1980-11-17 1984-03-13 International Business Machines Corporation Cache memory architecture with decoding
US4464712A (en) * 1981-07-06 1984-08-07 International Business Machines Corporation Second level cache replacement method and apparatus
US4638426A (en) * 1982-12-30 1987-01-20 International Business Machines Corporation Virtual memory address translation mechanism with controlled data persistence
US4612612A (en) * 1983-08-30 1986-09-16 Amdahl Corporation Virtually addressed cache

Also Published As

Publication number Publication date
JPS5687282A (en) 1981-07-15
US4700291A (en) 1987-10-13
FR2472233A1 (fr) 1981-06-26
US4502110A (en) 1985-02-26
US4727484A (en) 1988-02-23

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