FR2405513A1 - Circuit generateur de phase de commande d'execution d'operations dans un systeme informatique - Google Patents

Circuit generateur de phase de commande d'execution d'operations dans un systeme informatique

Info

Publication number
FR2405513A1
FR2405513A1 FR7730299A FR7730299A FR2405513A1 FR 2405513 A1 FR2405513 A1 FR 2405513A1 FR 7730299 A FR7730299 A FR 7730299A FR 7730299 A FR7730299 A FR 7730299A FR 2405513 A1 FR2405513 A1 FR 2405513A1
Authority
FR
France
Prior art keywords
level
phase generator
computer system
input
generator circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7730299A
Other languages
English (en)
Other versions
FR2405513B1 (fr
Inventor
Andre Richard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SA
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Priority to FR7730299A priority Critical patent/FR2405513A1/fr
Priority to US05/941,689 priority patent/US4262219A/en
Priority to GB7838076A priority patent/GB2011210B/en
Publication of FR2405513A1 publication Critical patent/FR2405513A1/fr
Application granted granted Critical
Publication of FR2405513B1 publication Critical patent/FR2405513B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
  • Networks Using Active Elements (AREA)

Abstract

Pour qu'un générateur de phase réponde à deux modes d'activation selon que l'une ou l'autre de deux tensions d'entrée est en avance ou en retard sur l'autre en leurs transitions d'un sens déterminé d'un premier niveau de tension à un second niveau. Le circuit incorpore un montage d'entrée ne se débloquant pour activer un montage de sortie à deux niveaux de tension que lorsqu'une transition de sens défini dans l'une des tensions s'effectue après qu'une transition de sens défini se soit produite dans l'autre des tensions, l'ordre de ces transitions étant indifférent au résultat requis. Ce déblocage assure un trajet de décharge d'un noeud de potentiel pré-chargé et relié par un suiveur-adaptateur de niveaux à une entrée d'activation du montage de sortie. Applications : générateurs de phase de commande d'opérations dans les systemes informatiques.
FR7730299A 1977-10-07 1977-10-07 Circuit generateur de phase de commande d'execution d'operations dans un systeme informatique Granted FR2405513A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR7730299A FR2405513A1 (fr) 1977-10-07 1977-10-07 Circuit generateur de phase de commande d'execution d'operations dans un systeme informatique
US05/941,689 US4262219A (en) 1977-10-07 1978-09-12 Circuit for generating phases to control the carrying out of operations in a data processing system
GB7838076A GB2011210B (en) 1977-10-07 1978-09-25 Circuit for generating phases to control the carrying out of operations in a data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7730299A FR2405513A1 (fr) 1977-10-07 1977-10-07 Circuit generateur de phase de commande d'execution d'operations dans un systeme informatique

Publications (2)

Publication Number Publication Date
FR2405513A1 true FR2405513A1 (fr) 1979-05-04
FR2405513B1 FR2405513B1 (fr) 1980-04-18

Family

ID=9196268

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7730299A Granted FR2405513A1 (fr) 1977-10-07 1977-10-07 Circuit generateur de phase de commande d'execution d'operations dans un systeme informatique

Country Status (3)

Country Link
US (1) US4262219A (fr)
FR (1) FR2405513A1 (fr)
GB (1) GB2011210B (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922138A (en) * 1987-05-25 1990-05-01 Canon Kabushiki Kaisha Scan circuit using a plural bootstrap effect for forming scan pulses
US6097618A (en) * 1997-12-11 2000-08-01 Cypress Semiconductor Corporation Apparatus and method for correcting data in a non-volatile random access memory
US8072834B2 (en) * 2005-08-25 2011-12-06 Cypress Semiconductor Corporation Line driver circuit and method with standby mode of operation
US7859925B1 (en) 2006-03-31 2010-12-28 Cypress Semiconductor Corporation Anti-fuse latch self-test circuit and method
US7859906B1 (en) 2007-03-30 2010-12-28 Cypress Semiconductor Corporation Circuit and method to increase read margin in non-volatile memories using a differential sensing circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3778784A (en) * 1972-02-14 1973-12-11 Intel Corp Memory system incorporating a memory cell and timing means on a single semiconductor substrate
US3868657A (en) * 1972-08-28 1975-02-25 Motorola Inc Peripheral circuitry for dynamic mos rams
US3835457A (en) * 1972-12-07 1974-09-10 Motorola Inc Dynamic mos ttl compatible
US3859637A (en) * 1973-06-28 1975-01-07 Ibm On-chip auxiliary latch for down-powering array latch decoders
US3964030A (en) * 1973-12-10 1976-06-15 Bell Telephone Laboratories, Incorporated Semiconductor memory array
US3906464A (en) * 1974-06-03 1975-09-16 Motorola Inc External data control preset system for inverting cell random access memory
US4087704A (en) * 1974-11-04 1978-05-02 Intel Corporation Sequential timing circuitry for a semiconductor memory
US4021656A (en) * 1974-11-19 1977-05-03 Texas Instruments Incorporated Data input for electronic calculator or digital processor chip
US4061933A (en) * 1975-12-29 1977-12-06 Mostek Corporation Clock generator and delay stage
US4038646A (en) * 1976-03-12 1977-07-26 Intel Corporation Dynamic mos ram

Also Published As

Publication number Publication date
GB2011210A (en) 1979-07-04
FR2405513B1 (fr) 1980-04-18
US4262219A (en) 1981-04-14
GB2011210B (en) 1982-06-16

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