JPS5782282A - Booster and memory device using it - Google Patents

Booster and memory device using it

Info

Publication number
JPS5782282A
JPS5782282A JP55155948A JP15594880A JPS5782282A JP S5782282 A JPS5782282 A JP S5782282A JP 55155948 A JP55155948 A JP 55155948A JP 15594880 A JP15594880 A JP 15594880A JP S5782282 A JPS5782282 A JP S5782282A
Authority
JP
Japan
Prior art keywords
phix
time
leading
line
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55155948A
Other languages
Japanese (ja)
Inventor
Takashi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55155948A priority Critical patent/JPS5782282A/en
Publication of JPS5782282A publication Critical patent/JPS5782282A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To decrease the operation cycle of an RAM, by separating a bootstrap capacitance of large capacity from a common data line at the time of leading edge of a word control signal, and at the same time precharging it with other MISFET during boosting. CONSTITUTION:A MISFETT51 applying a power supply voltage vcc to the gate is provided between an output line of a pulse generating circuit phix-GENE provided on a common word line and a connecting point N1 in a booster circuit phix- BOOS, a bootstrap capacitance CB21 is given between connecting points N2, N1 to which a pulse signal phipad delayed for the leading time from the word line control signal phix, and an MISFETT52 the gate of which is a voltage of N1 is applied is provided between the output line and a connecting point N3 respectively. A CB22 between the N2 and N3 is precharged at the reference potential signal level period of the pulse signal at the N2 with a switching element T53 between the N3 and the power supply voltage Vcc. Thus, since the CB22 of comparatively large capacity is separated from the common data line at the time of leading edge of the phix, the leading speed of the phix is quickened and the operation cycle of an RAM is shortened.
JP55155948A 1980-11-07 1980-11-07 Booster and memory device using it Pending JPS5782282A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55155948A JPS5782282A (en) 1980-11-07 1980-11-07 Booster and memory device using it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55155948A JPS5782282A (en) 1980-11-07 1980-11-07 Booster and memory device using it

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP63028663A Division JPS63308793A (en) 1988-02-12 1988-02-12 Memory device
JP63175031A Division JPH0264991A (en) 1988-07-15 1988-07-15 Memory

Publications (1)

Publication Number Publication Date
JPS5782282A true JPS5782282A (en) 1982-05-22

Family

ID=15617020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55155948A Pending JPS5782282A (en) 1980-11-07 1980-11-07 Booster and memory device using it

Country Status (1)

Country Link
JP (1) JPS5782282A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6011320U (en) * 1983-07-05 1985-01-25 旭硝子株式会社 light control body
JPS60107857A (en) * 1983-11-14 1985-06-13 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Voltage generating circuit in integrated circuit chip

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55136723A (en) * 1979-04-11 1980-10-24 Mitsubishi Electric Corp Booster circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55136723A (en) * 1979-04-11 1980-10-24 Mitsubishi Electric Corp Booster circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6011320U (en) * 1983-07-05 1985-01-25 旭硝子株式会社 light control body
JPH0228500Y2 (en) * 1983-07-05 1990-07-31
JPS60107857A (en) * 1983-11-14 1985-06-13 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Voltage generating circuit in integrated circuit chip
JPH0533480B2 (en) * 1983-11-14 1993-05-19 Intaanashonaru Bijinesu Mashiinzu Corp

Similar Documents

Publication Publication Date Title
KR0172337B1 (en) Semiconductor memory device
GB1523080A (en) Fet delay circuits
GB1525810A (en) Clock generator and delay stage
JPS6437797A (en) Eprom device
EP0129661A3 (en) Bootstrap driver circuits for a mos memory
KR970703600A (en) A CONSTANT IMPEDANCE SAMPLING SWITCH
KR950030341A (en) Boost strap circuit of semiconductor device
JPH097374A (en) Data output buffer of semiconductor memory device
IE813069L (en) Buffer circuit
KR890007296A (en) Semiconductor integrated circuit device
KR940704079A (en) Ascended Voltage Generating Apparatus
JPS61175995A (en) Precharge clock signal generation circuit
KR860008561A (en) Booster circuit
US3660684A (en) Low voltage level output driver circuit
JPS5782282A (en) Booster and memory device using it
KR890017704A (en) Spare Column (COLUMN) Selection Method and Circuit
JPS55136723A (en) Booster circuit
GB1453708A (en) Driver pulse circuit
US4060740A (en) Sensing amplifier for capacitive MISFET memory
US4897559A (en) Variable clock delay circuit utilizing the R-C time constant
KR970029837A (en) Memory device having boost circuit and boost circuit control method
JPS59169B2 (en) flip flop circuit
JPS56111188A (en) Semiconductor storage device
JPS533049A (en) Logical circuit
DE3878784D1 (en) SEMICONDUCTOR MEMORY WITH A SIGNAL CHANGE DETECTION CIRCUIT.