FR2400209A1 - Appareil destine a realiser des essais fonctionnels de circuits electroniques - Google Patents
Appareil destine a realiser des essais fonctionnels de circuits electroniquesInfo
- Publication number
- FR2400209A1 FR2400209A1 FR7809154A FR7809154A FR2400209A1 FR 2400209 A1 FR2400209 A1 FR 2400209A1 FR 7809154 A FR7809154 A FR 7809154A FR 7809154 A FR7809154 A FR 7809154A FR 2400209 A1 FR2400209 A1 FR 2400209A1
- Authority
- FR
- France
- Prior art keywords
- registers
- operation memory
- large number
- memory circuit
- inputs connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Cet appareil comporte, pour chaque borne 3 d'un circuit électronique 4 à essayer, un bloc 6 de stockage et de sortie de séquences codées de valeurs de contrôle et de consigne des signaux, ce bloc comprenant deux registres de décalage 22, 23, un registre de décalage à trois bits 16 connecté à la borne 3 à essayer une mémoire 26 reliée aux entrées 27, 28 des registres de décalage 22, 23 et un registre d'adresse 29 relié à l'entrée 30 de la mémoire 26. L'appareil comporte un bloc 7 de définition des régimes commun aux bornes 3 à essayer et comportant un circuit de commande 48, un circuit 47 mémorisant les régimes, des registres d'adresse de départ 42, d'adresse finale 43, de microcycles 44, de cycles 45 et d'impulsions de synchronisation 46 connectés aux circuits 47 et 48, un circuit de comparaison 31 dont l'entrée 69 est reliée à la sortie 68 du registre d'adresse finale 43, l'entrée 32 étant reliée à la sortie du registre d'adresse 29 ainsi qu'un circuit d'écriture 33 connecté avec le circuit de commande 48, les sorties 34 du circuit 33 étant reliées aux entrées séparées du registre d'adresse 29, de la mémoire 26, des registres de décalage 22, 23, des portes ET-OU 19, 20 et du registre de décalage 16 à trois bits.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SU772472761A SU802970A1 (ru) | 1977-04-08 | 1977-04-08 | Устройство дл функционального конт-РОл бОльшиХ иНТЕгРАльНыХ CXEM |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2400209A1 true FR2400209A1 (fr) | 1979-03-09 |
FR2400209B1 FR2400209B1 (fr) | 1982-10-15 |
Family
ID=20703602
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7809154A Granted FR2400209A1 (fr) | 1977-04-08 | 1978-03-29 | Appareil destine a realiser des essais fonctionnels de circuits electroniques |
Country Status (8)
Country | Link |
---|---|
BG (1) | BG41621A1 (fr) |
DD (1) | DD136771A1 (fr) |
FR (1) | FR2400209A1 (fr) |
GR (1) | GR64070B (fr) |
HU (1) | HU177211B (fr) |
IT (1) | IT7841558A0 (fr) |
PL (1) | PL121435B1 (fr) |
SU (1) | SU802970A1 (fr) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2036316A7 (fr) * | 1969-03-10 | 1970-12-24 | Gaillard Edmond | |
US3790885A (en) * | 1972-03-27 | 1974-02-05 | Ibm | Serial test patterns for mosfet testing |
US3924144A (en) * | 1973-05-11 | 1975-12-02 | Ibm | Method for testing logic chips and logic chips adapted therefor |
US3976940A (en) * | 1975-02-25 | 1976-08-24 | Fairchild Camera And Instrument Corporation | Testing circuit |
US4000460A (en) * | 1974-07-01 | 1976-12-28 | Xerox Corporation | Digital circuit module test system |
-
1977
- 1977-04-08 SU SU772472761A patent/SU802970A1/ru active
-
1978
- 1978-02-01 BG BG7838552A patent/BG41621A1/xx unknown
- 1978-03-28 GR GR55815A patent/GR64070B/el unknown
- 1978-03-29 FR FR7809154A patent/FR2400209A1/fr active Granted
- 1978-04-04 PL PL1978205799A patent/PL121435B1/pl unknown
- 1978-04-06 IT IT7841558A patent/IT7841558A0/it unknown
- 1978-04-06 HU HU78GA1250A patent/HU177211B/hu not_active IP Right Cessation
- 1978-04-06 DD DD78204633A patent/DD136771A1/xx not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2036316A7 (fr) * | 1969-03-10 | 1970-12-24 | Gaillard Edmond | |
US3790885A (en) * | 1972-03-27 | 1974-02-05 | Ibm | Serial test patterns for mosfet testing |
US3924144A (en) * | 1973-05-11 | 1975-12-02 | Ibm | Method for testing logic chips and logic chips adapted therefor |
US4000460A (en) * | 1974-07-01 | 1976-12-28 | Xerox Corporation | Digital circuit module test system |
US3976940A (en) * | 1975-02-25 | 1976-08-24 | Fairchild Camera And Instrument Corporation | Testing circuit |
Also Published As
Publication number | Publication date |
---|---|
GR64070B (en) | 1980-01-21 |
PL121435B1 (en) | 1982-05-31 |
SU802970A1 (ru) | 1981-02-07 |
IT7841558A0 (it) | 1978-04-06 |
PL205799A1 (pl) | 1979-01-15 |
HU177211B (en) | 1981-08-28 |
DD136771A1 (de) | 1979-07-25 |
BG41621A1 (en) | 1987-07-15 |
FR2400209B1 (fr) | 1982-10-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |