FR2307400A1 - Procede et circuit pour la demodulation de signaux a phase divisee enregistres en serie sur bande magnetique - Google Patents
Procede et circuit pour la demodulation de signaux a phase divisee enregistres en serie sur bande magnetiqueInfo
- Publication number
- FR2307400A1 FR2307400A1 FR7610586A FR7610586A FR2307400A1 FR 2307400 A1 FR2307400 A1 FR 2307400A1 FR 7610586 A FR7610586 A FR 7610586A FR 7610586 A FR7610586 A FR 7610586A FR 2307400 A1 FR2307400 A1 FR 2307400A1
- Authority
- FR
- France
- Prior art keywords
- phase
- split
- bit rate
- reproduced signal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 title abstract 3
- 238000000034 method Methods 0.000 abstract 3
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DD18533075A DD124408A3 (enExample) | 1975-04-09 | 1975-04-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2307400A1 true FR2307400A1 (fr) | 1976-11-05 |
| FR2307400B3 FR2307400B3 (enExample) | 1979-07-13 |
Family
ID=5499862
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7610586A Granted FR2307400A1 (fr) | 1975-04-09 | 1976-04-09 | Procede et circuit pour la demodulation de signaux a phase divisee enregistres en serie sur bande magnetique |
Country Status (6)
| Country | Link |
|---|---|
| CS (1) | CS208367B1 (enExample) |
| DD (1) | DD124408A3 (enExample) |
| DE (1) | DE2610687A1 (enExample) |
| FR (1) | FR2307400A1 (enExample) |
| NL (1) | NL7603667A (enExample) |
| SU (1) | SU665319A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2482802A1 (fr) * | 1980-05-14 | 1981-11-20 | Magyar Optikai Muevek | Dispositif electronique de decodage d'informations pour un dispositif fonctionnant en auto-synchronisation |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ZA81781B (en) * | 1980-02-13 | 1982-03-31 | Int Computers Ltd | Digital systems |
-
1975
- 1975-04-09 DD DD18533075A patent/DD124408A3/xx unknown
-
1976
- 1976-03-13 DE DE19762610687 patent/DE2610687A1/de not_active Withdrawn
- 1976-04-02 CS CS216576A patent/CS208367B1/cs unknown
- 1976-04-07 NL NL7603667A patent/NL7603667A/xx not_active Application Discontinuation
- 1976-04-09 FR FR7610586A patent/FR2307400A1/fr active Granted
- 1976-04-09 SU SU762344806A patent/SU665319A1/ru active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2482802A1 (fr) * | 1980-05-14 | 1981-11-20 | Magyar Optikai Muevek | Dispositif electronique de decodage d'informations pour un dispositif fonctionnant en auto-synchronisation |
Also Published As
| Publication number | Publication date |
|---|---|
| SU665319A1 (ru) | 1979-05-30 |
| DE2610687A1 (de) | 1977-01-20 |
| DD124408A3 (enExample) | 1977-02-23 |
| FR2307400B3 (enExample) | 1979-07-13 |
| NL7603667A (nl) | 1976-10-12 |
| CS208367B1 (en) | 1981-09-15 |
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