DD124408A3 - - Google Patents

Info

Publication number
DD124408A3
DD124408A3 DD18533075A DD18533075A DD124408A3 DD 124408 A3 DD124408 A3 DD 124408A3 DD 18533075 A DD18533075 A DD 18533075A DD 18533075 A DD18533075 A DD 18533075A DD 124408 A3 DD124408 A3 DD 124408A3
Authority
DD
German Democratic Republic
Application number
DD18533075A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to DD18533075A priority Critical patent/DD124408A3/xx
Priority to DE19762610687 priority patent/DE2610687A1/de
Priority to CS216576A priority patent/CS208367B1/cs
Priority to NL7603667A priority patent/NL7603667A/xx
Priority to FR7610586A priority patent/FR2307400A1/fr
Priority to SU762344806A priority patent/SU665319A1/ru
Publication of DD124408A3 publication Critical patent/DD124408A3/xx

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/14Digital recording or reproducing using self-clocking codes
    • G11B20/1403Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
DD18533075A 1975-04-09 1975-04-09 DD124408A3 (xx)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DD18533075A DD124408A3 (xx) 1975-04-09 1975-04-09
DE19762610687 DE2610687A1 (de) 1975-04-09 1976-03-13 Verfahren zur demodulation von auf magnetband seriell aufgezeichneten split- phase-signalen und schaltungsanordnung zur durchfuehrung des verfahrens
CS216576A CS208367B1 (en) 1975-04-09 1976-04-02 Method of demodulation of the,by series recorded signals with the divided phase on the moving magnetic memory code and connection for executing the same
NL7603667A NL7603667A (nl) 1975-04-09 1976-04-07 Werkwijze en inrichting voor het demoduleren van in serie op een magneetband opgetekende split- -phase-signalen.
FR7610586A FR2307400A1 (fr) 1975-04-09 1976-04-09 Procede et circuit pour la demodulation de signaux a phase divisee enregistres en serie sur bande magnetique
SU762344806A SU665319A1 (ru) 1975-04-09 1976-04-09 Способ демодул ции воспроизведенного фазомодулированного сигнала и устройство дл его осуществлени

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DD18533075A DD124408A3 (xx) 1975-04-09 1975-04-09

Publications (1)

Publication Number Publication Date
DD124408A3 true DD124408A3 (xx) 1977-02-23

Family

ID=5499862

Family Applications (1)

Application Number Title Priority Date Filing Date
DD18533075A DD124408A3 (xx) 1975-04-09 1975-04-09

Country Status (6)

Country Link
CS (1) CS208367B1 (xx)
DD (1) DD124408A3 (xx)
DE (1) DE2610687A1 (xx)
FR (1) FR2307400A1 (xx)
NL (1) NL7603667A (xx)
SU (1) SU665319A1 (xx)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ZA81781B (en) * 1980-02-13 1982-03-31 Int Computers Ltd Digital systems
HU183139B (en) * 1980-05-14 1984-04-28 Magyar Optikai Muevek Electronic decoding circuit arrangement for systems with self-synchronization

Also Published As

Publication number Publication date
FR2307400A1 (fr) 1976-11-05
NL7603667A (nl) 1976-10-12
SU665319A1 (ru) 1979-05-30
FR2307400B3 (xx) 1979-07-13
DE2610687A1 (de) 1977-01-20
CS208367B1 (en) 1981-09-15

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