HU183139B - Electronic decoding circuit arrangement for systems with self-synchronization - Google Patents

Abstract

To increase the density of magnetic recording it is desirable to minimise the number of flux transitions used to identify each bit of data whilst maintaining self synchronisation. The decoder uses a defined time base and compares this with the input signal at defined instants using logic circuits and a frequency modification coding. The circuit has compensation inputs to accommodate for variations such as speed and temperature. The input signal transitions are converted into short duration pulses which synchronise a sawtooth generator. This waveform is supplied to one input of each of four comparators. The other comparator inputs are provided by a control circuit via a resistor divider chain. Compensation inputs to this circuit provide reference voltage changes for such things as temperature and speed variations. The comparator outputs provide a short pulse at the start of each transition window and a data valid pulse. The data output is provided by two bistables. The first one toggles every time an input pulse is not detected within a data bit period.

Description

BACKGROUND OF THE INVENTION The present invention relates to an electronic decoding circuit arrangement for self-synchronizing systems, in particular for digital information storage devices operating on the principle of moving magnetic signal recording or for wired systems.

The vast majority of digital information storage devices used in computing are based on the principle of thin-layer motion magnetic recording. The high degree of practical penetration is due to the low unit cost per bit and its flexible applicability. Further improvement of these indicators of information storage devices can be achieved by better utilization of the magnetic storage layer (later referred to as a carrier) and by increasing the amount of information that can be placed per unit area. One way of doing this is by sequentially compressing the magnetic transitions recorded as serial information transformations. This is limited by the extent of signal distortion during reading and by the physical-mechanical characteristics of the carrier and the writer-reader head. ___

While reading from storage media, with the emphasis on self-synchronization, various information coding methods have been developed that require fewer magnetic transitions to record one bit of information.

Such coding methods include various frequency or phase modulation methods, and combinations thereof. As coding techniques evolved, they sought to reduce coding redundancy. This redundancy results from the combination of validation signals and information content needed to ensure self-synchronization.

While the first used FM (frequency mode) and DFM (double frequency mode) encoding is 100% redundancy, which means that each information bit is captured with a validation signal (maximum two magnetic transitions per bit cell), while the MFM) ( 50% for modified frequency mode) and 10-20% for modified non retum to zero inverter (MNRZ-I).

The read signal (coded below) coded by the aforementioned methods or their various modes can be divided into two parts, namely an information-containing binary electronic signal (hereinafter information) and an information impulse sequence (hereinafter validation signal). The information and the validation signal, as well as their relationship, are provided by the pulse timing of the read signal. During writing and reading, these time conditions are distorted. The function of the decoding circuit is to evaluate and separate the signals thus loaded with distortion. A circuit design suitable for decoding the most distorted signals is also desirable. A decoding circuit approaches its maximum efficiency when it is able to take full advantage of its window size (expected time of signal reception), which is characterized by maximum allowable distortion of signals to perform its function.

In order to increase the write density, which clearly results in the improvement of the technical and economic parameters of the storage device, coding methods that work with low redundancy are becoming more and more prominent. Decoding these sequences with more complex and tighter tolerances (narrower window size) requires the design of optimally designed decoding layouts.

The decoding circuit layouts perform their function by restoring the original information signal and the validation signal using a logical network by selecting a specific time base and comparing the read signal repetition time and their ratios.

By examining these solutions, the following disadvantages can be identified.

The common working principle of different decoding circuit arrangements based on direct time comparison is to generate reference times with some timing element or elements, preferably monostable multivibrators, to which the time intervals of the read signal pulses are directly compared (e.g., in sequence).

The timing elements are triggered by pulses of the read signal. In the case of efficient coding methods, the theoretical locations of the pulse spacing can vary. For example, in MFM coding, the time intervals of consecutive pulses are equal to 1-1.5 bit cells. Thus, due to operation, the timing elements may be triggered from either a basic state or a working state when the reference time to be generated by it has not yet expired. Due to the necessity of the two startup modes, the time output is not equal to each other, thus reducing the window size by this time difference.

Also, decoding circuit arrangements using different sampling methods are known, but in these solutions, the window size decreases with the entire period of sampling time.

It is an object of the present invention to provide a decoding circuit arrangement that overcomes the drawbacks of the prior art and allows for decoding-free and adaptable decoding of multiple systems.

The outputs of a voltage generator for generating reference levels in a circuit arrangement according to the invention are connected to an input of a voltage comparator and a pulse generator having a plurality of comparator levels, its output is coupled to an input of a validation separator network and a first input of an information separator network, the second input of which is connected to an intermediate output of a voltage comparator and a pulse generator.

Converts a read signal sequence containing encoded information to a pulse generator constant pulse width signal sequence. The minimum value of the pulse width is determined by the progress of various transient phenomena (such as the time required to restart timers; the encoder reset, etc.), and its maximum value is determined by half the window size. During the pulse, the timer or other elements of the decoding circuit, which may reduce the window size, are reset to the same initial condition. This constant time can in any case be incorporated in the further circuitry of the decoder.

This provides one of the conceptual and practical advantages of this circuit layout over all previous solutions, since it provides 100% utilization of the theoretically available window size. so the decoder

183,139, and other elements of information recording or transmission, such as writers, readers, storage layers, power lines, and the like. - the amount of distortion it enters can be larger, which allows it to either be simpler and cheaper to build, or allows for a higher load - higher transmission frequency, denser write - up.

The invention will now be described in more detail with reference to an embodiment and drawings. In the drawing it is

Figure 1 is an embodiment of an MFM coded read signal decoding network,

Figure 2 is a time diagram of the circuit, and

Figure 3 shows the position of the pulses with the window dimensions and the output signal of the time-to-voltage converter. According to Fig. 1, the pulse sequence containing the coded information OFF arrives at the pulse generator 1, where it passes directly to one of the inputs of the OR gate Z2, and to the inverter Z1 and the other input of the gate Z2 via the delay line. The output of gate Z2 OR, which is also the output of pulse generator 1, gives a pulse width KIF pulse sequence τ.

The resistors R1-R2 perform the matching of the delay line τ 1. The high level of the KIF pulse series, which passes to the time-to-voltage converter 2, causes the transistor T1 to conduct, which discharges capacitor C, and from the transistor T2, R3-R4-R5, e.g. a current generator current formed from a potentiometer, a temperature compensating diode D1, and a filter capacitor C1. The discharge process is very fast (10-20 sec), and since the pulses of the KIF pulse series are wider, capacitor C is discharged in all cases to the residual voltage of the TI transistor. When the TI transistor is closed, the aforementioned current generator charges the capacitor C. The current of the current generator and thus of the voltage ramp of the capacitor C can be set using the potentiometer P1. The emitter-tracking circuit formed by transistor T3 and resistor R6 isolates the load effect of voltage comparator 4 and pulse generator network from capacitor C. The reference voltages of the voltage comparator 4 and of the pulse generator network containing the comparators Z5-Z8 are provided by a reference voltage generator 3 with suitably different correction inputs (temperature, speed, etc.). The active elements of the reference voltage generator 3 are the operation amplifiers Z3 with the resistors R10-R11 and the operational amplifiers Z4 with the resistors R12-R13. Operational amplifiers Z3-Z4 are connected to the - U _V ez and + U _V ez correction inputs with adjustable resistors P2-R8 and P3-R9, respectively. The outputs of the operational amplifiers Z3-Z4 are connected to a network of five resistors (1 / 8R, 2 / 8R. 2 / 8R, 2 / 8R, 1 / 8R), the outlets of which are the outputs of the reference voltage generator 3. The reference voltages U _r , -U _r4 , i.e. the distribution circuit of the reference voltage generator 3, are set according to the following considerations:

In each case, the number and value of the reference levels are determined by the coding characteristics. In the case of the exemplary MFM decoding, this results in four voltage values. In MFM coding, the theoretical time span of the read signal pulses is 1; 1.5; 2 bit cell time. In order to be able to evaluate each pulse representing magnetic change, each window size limit must be selected. Its expected position is symmetrical to the rising edges of the pulses of the read signal without distortion. The reference levels defining the location of the nth pulse, the expected locations of the (N + 1) pulse, and the quasi-triangular voltage Uc obtained after the time-voltage conversion and the window size limits H are shown in Figure 3. It can also be seen that the reference _voltages UR, -U _{r4 are} 1/8; 3/8; 5/8; 7/8 division ratio can resistor chain (Figure 1), if the transfer _pipe is connected U DC. U _r U _r4 correction reference voltage inputs of the correction made EZ2 _vezi U + U and _V, as appropriate ratio of the change in each Un appears in _U-r4 reference voltage. Figure 3 also shows the pulse width τ and the bit cell time Tg.

In the voltage comparator 4 and pulse generator network, short-term pulses are generated from the rising edges of the Z5-Z8 comparators by the Z9-Z11-Z13-Z15 inverters, the Z10-Z12-Z14-Z16 dual-input AND-NO gates and the Z17 four-input help. The pulse sequence displayed at the output of the Z17 four-input AND NO gate is such that the pulse repetition time is half the repetition time of the validation signal at the ARV output of the validator separation network 5. This signal is appropriately divided by the Z18 bistable multivibrator to obtain a rectangular signal having two ruptured edges, which comprise a monostable multivibrator pulse formed by an inverter Z21, an integrating member consisting of a resistor R7 and a capacitor C2, and a dual-input AND-NOT gate Z22. The Z22 dual-input AND-NO gate output provides the pulse sequence which is the signal of the EVR output and is also an output signal of the decoder. The proper phase of the split signal is provided by the timing of the external signal to the ENG reset input.

The information separation network 6 consists of bistable multivibrators Z19-Z20. The Z19 bistable multivibrator tilts each time the read signal pulses are absent for at least 1 bit cell, meaning there is a change in information due to encoding. This condition was recognized by the decoder from the high state of the Z7 comparator - signal B. The Z19 bistable multivibrator in high state clears the Z20 bistable multivibrator through cl input (asynchronously), while the Z19 bistable multivibrator low allows the Z20 multivibrator to enter a high level on the controller inputs (synchronously). The output of the Z20 bistable multivibrator displays the decoded I information and the other output of the decoder. These major waveforms are shown in Figure 2.

Claims (3)

Patent claims 1. Electronic decoding circuit arrangement for self-synchronizing systems, in particular for digital information storage devices or wired systems, based on the principle of moving magnetic signal recording, comprising circuits consisting of passive elements and active semiconductors, characterized by the generation of reference voltages 3 connected to each other its outputs are connected to the input of voltage comparator and pulse generator (4) with several comparator levels, and can be started with coded input signal 183,139 The output of the pulse generator (1) of FIG. 3 is connected to the input of a time-voltage converter (2), the output of which is connected to a further input of the voltage comparator and pulse generator (4). The second input is connected to the intermediate output of the voltage comparator and the pulse generator (4). An embodiment of a circuit arrangement according to claim 1, characterized in that the reference voltage generator (3) is provided with correction inputs (U _V i U U U _V 2 2). Embodiment of the circuit arrangement according to claim 1 or 2, characterized in that the information decoupling network (6) and / or the validation signal isolation network (5) has a reset input (ENG).