FR2307400A1 - Split-phase signal demodulator - includes null detector having pulse output applied to sampling circuit - Google Patents

Split-phase signal demodulator - includes null detector having pulse output applied to sampling circuit

Info

Publication number
FR2307400A1
FR2307400A1 FR7610586A FR7610586A FR2307400A1 FR 2307400 A1 FR2307400 A1 FR 2307400A1 FR 7610586 A FR7610586 A FR 7610586A FR 7610586 A FR7610586 A FR 7610586A FR 2307400 A1 FR2307400 A1 FR 2307400A1
Authority
FR
France
Prior art keywords
phase
split
bit rate
reproduced signal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7610586A
Other languages
French (fr)
Other versions
FR2307400B3 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zentronik VEB
Original Assignee
Zentronik VEB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zentronik VEB filed Critical Zentronik VEB
Publication of FR2307400A1 publication Critical patent/FR2307400A1/en
Application granted granted Critical
Publication of FR2307400B3 publication Critical patent/FR2307400B3/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

A method for the demodulation of split-phase signals recorded in sequence on a magnetic tape, applicable to the processing of recording of instrumental readings or of digital information using split phase mark or split phase change techniques. The information content is derived with improved signal to noise ratio and the method is easily adaptable to a different bit rate without necessitating any change in the phase of the reproduced signal. Demodulation is effected by sampling the reproduced signal using a bit rate of suitable phase setting, the information content being recovered through a logic coupling of pairs of successively sampled symbol values, the bit rate being derived by sampling of a sawtooth signal at the zero transits of the reproduced signal to obtain a control voltage which controls a voltage-controlled oscillator through a filter. The oscillator is thus brought into appredetermined phase in relation to the recorded binary pulse series.
FR7610586A 1975-04-09 1976-04-09 Split-phase signal demodulator - includes null detector having pulse output applied to sampling circuit Granted FR2307400A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DD18533075A DD124408A3 (en) 1975-04-09 1975-04-09

Publications (2)

Publication Number Publication Date
FR2307400A1 true FR2307400A1 (en) 1976-11-05
FR2307400B3 FR2307400B3 (en) 1979-07-13

Family

ID=5499862

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7610586A Granted FR2307400A1 (en) 1975-04-09 1976-04-09 Split-phase signal demodulator - includes null detector having pulse output applied to sampling circuit

Country Status (6)

Country Link
CS (1) CS208367B1 (en)
DD (1) DD124408A3 (en)
DE (1) DE2610687A1 (en)
FR (1) FR2307400A1 (en)
NL (1) NL7603667A (en)
SU (1) SU665319A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2482802A1 (en) * 1980-05-14 1981-11-20 Magyar Optikai Muevek Self synchronising data decoder for modified frequency recording - uses voltage ramp generated by input transitions fed to bank of comparators to generate data output and data valid signals

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ZA81781B (en) * 1980-02-13 1982-03-31 Int Computers Ltd Digital systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2482802A1 (en) * 1980-05-14 1981-11-20 Magyar Optikai Muevek Self synchronising data decoder for modified frequency recording - uses voltage ramp generated by input transitions fed to bank of comparators to generate data output and data valid signals

Also Published As

Publication number Publication date
NL7603667A (en) 1976-10-12
SU665319A1 (en) 1979-05-30
DD124408A3 (en) 1977-02-23
FR2307400B3 (en) 1979-07-13
DE2610687A1 (en) 1977-01-20
CS208367B1 (en) 1981-09-15

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