FR2295568A1 - Procede de depot heteroepitaxique pour la realisation de diodes gap/si - Google Patents

Procede de depot heteroepitaxique pour la realisation de diodes gap/si

Info

Publication number
FR2295568A1
FR2295568A1 FR7532220A FR7532220A FR2295568A1 FR 2295568 A1 FR2295568 A1 FR 2295568A1 FR 7532220 A FR7532220 A FR 7532220A FR 7532220 A FR7532220 A FR 7532220A FR 2295568 A1 FR2295568 A1 FR 2295568A1
Authority
FR
France
Prior art keywords
heteroepitaxic
diodes
realization
gap
deposit process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7532220A
Other languages
English (en)
Other versions
FR2295568B1 (fr
Inventor
Robert W Broadie
Bernard M Kemlage
Hans B Pogge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2295568A1 publication Critical patent/FR2295568A1/fr
Application granted granted Critical
Publication of FR2295568B1 publication Critical patent/FR2295568B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02461—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/025—Deposition multi-step
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/059—Germanium on silicon or Ge-Si on III-V
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/067—Graded energy gap
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/072—Heterojunctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/119—Phosphides of gallium or indium
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Led Devices (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
FR7532220A 1974-12-17 1975-10-13 Procede de depot heteroepitaxique pour la realisation de diodes gap/si Granted FR2295568A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/533,604 US3963538A (en) 1974-12-17 1974-12-17 Two stage heteroepitaxial deposition process for GaP/Si

Publications (2)

Publication Number Publication Date
FR2295568A1 true FR2295568A1 (fr) 1976-07-16
FR2295568B1 FR2295568B1 (fr) 1979-05-04

Family

ID=24126690

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7532220A Granted FR2295568A1 (fr) 1974-12-17 1975-10-13 Procede de depot heteroepitaxique pour la realisation de diodes gap/si

Country Status (5)

Country Link
US (1) US3963538A (fr)
JP (1) JPS5820151B2 (fr)
DE (1) DE2549787C2 (fr)
FR (1) FR2295568A1 (fr)
GB (1) GB1501736A (fr)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856963B2 (ja) * 1977-05-06 1983-12-17 三菱化成ポリテック株式会社 電子発光化合物半導体の製造方法
US4148045A (en) * 1977-09-21 1979-04-03 International Business Machines Corporation Multicolor light emitting diode array
JPS581539B2 (ja) * 1978-07-07 1983-01-11 三菱化成ポリテック株式会社 エピタキシヤルウエハ−
FR2435816A1 (fr) * 1978-09-08 1980-04-04 Radiotechnique Compelec Procede de realisation, par epitaxie, d'un dispositif semi-conducteur a structure multicouches et application de ce procede
FR2447612A1 (fr) * 1979-01-26 1980-08-22 Thomson Csf Composant semi-conducteur a heterojonction
US4517047A (en) * 1981-01-23 1985-05-14 The United States Of America As Represented By The Secretary Of The Army MBE growth technique for matching superlattices grown on GaAs substrates
US4596626A (en) * 1983-02-10 1986-06-24 The United States Of America As Represented By The United States National Aeronautics And Space Administration Method of making macrocrystalline or single crystal semiconductor material
JPS6012724A (ja) * 1983-07-01 1985-01-23 Agency Of Ind Science & Technol 化合物半導体の成長方法
US5091333A (en) * 1983-09-12 1992-02-25 Massachusetts Institute Of Technology Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth
US4632712A (en) * 1983-09-12 1986-12-30 Massachusetts Institute Of Technology Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth
US4697202A (en) * 1984-02-02 1987-09-29 Sri International Integrated circuit having dislocation free substrate
US4588451A (en) * 1984-04-27 1986-05-13 Advanced Energy Fund Limited Partnership Metal organic chemical vapor deposition of 111-v compounds on silicon
US4548658A (en) * 1985-01-30 1985-10-22 Cook Melvin S Growth of lattice-graded epilayers
JPS61291491A (ja) * 1985-06-19 1986-12-22 Mitsubishi Monsanto Chem Co りん化ひ化ガリウム混晶エピタキシヤルウエハ
IL78840A0 (en) * 1985-10-17 1986-09-30 Holobeam Lattice-graded epilayer
US4891091A (en) * 1986-07-14 1990-01-02 Gte Laboratories Incorporated Method of epitaxially growing compound semiconductor materials
EP0297867B1 (fr) * 1987-07-01 1993-10-06 Nec Corporation Procédé pour la croissance d'un cristal semi-conducteur d'un composé III-V sur un substrat de Si
US5079616A (en) * 1988-02-11 1992-01-07 Gte Laboratories Incorporated Semiconductor structure
US5272105A (en) * 1988-02-11 1993-12-21 Gte Laboratories Incorporated Method of manufacturing an heteroepitaxial semiconductor structure
US5238869A (en) * 1988-07-25 1993-08-24 Texas Instruments Incorporated Method of forming an epitaxial layer on a heterointerface
JP2507888B2 (ja) * 1988-11-19 1996-06-19 工業技術院長 ヘテロ構造体の製造方法
US5075743A (en) * 1989-06-06 1991-12-24 Cornell Research Foundation, Inc. Quantum well optical device on silicon
CA2062134C (fr) * 1991-05-31 1997-03-25 Ibm Couches hétéroépitaxiales à faible densité de défauts et parmètre de réseau arbitraire
JP3436379B2 (ja) * 1992-07-28 2003-08-11 三菱化学株式会社 りん化ひ化ガリウムエピタキシャルウエハ
US6010937A (en) * 1995-09-05 2000-01-04 Spire Corporation Reduction of dislocations in a heteroepitaxial semiconductor structure
JP3268731B2 (ja) 1996-10-09 2002-03-25 沖電気工業株式会社 光電変換素子
US8148591B2 (en) * 2007-12-21 2012-04-03 Chevron Oronite Company Llc Method of making a synthetic alkylaryl compound

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USB524765I5 (fr) * 1966-02-03 1900-01-01
US3433684A (en) * 1966-09-13 1969-03-18 North American Rockwell Multilayer semiconductor heteroepitaxial structure
US3783009A (en) * 1971-02-22 1974-01-01 Air Reduction Method for improving perfection of epitaxially grown germanium films
US3699401A (en) * 1971-05-17 1972-10-17 Rca Corp Photoemissive electron tube comprising a thin film transmissive semiconductor photocathode structure
JPS52915B1 (fr) * 1971-06-01 1977-01-11
US3766447A (en) * 1971-10-20 1973-10-16 Harris Intertype Corp Heteroepitaxial structure
US3862859A (en) * 1972-01-10 1975-01-28 Rca Corp Method of making a semiconductor device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
REVUE US: "IBM TECHNICAL DISCLOSURE BULLETIN" *
SI DEPOSITION PROCESS WITH SELF-ISOLATED LIGHT-EMITTING DIODES" R.W. BROADIE ET H.B. POGGE, PAGE 1301.) *
VOLUME 16, NO. 4, SEPTEMBRE 1973 "SELECTIVE PLANAR GAP *

Also Published As

Publication number Publication date
GB1501736A (en) 1978-02-22
JPS5178187A (fr) 1976-07-07
DE2549787A1 (de) 1976-07-01
DE2549787C2 (de) 1984-04-12
US3963538A (en) 1976-06-15
FR2295568B1 (fr) 1979-05-04
JPS5820151B2 (ja) 1983-04-21

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