FR2290709A1 - Check word compared with data using bit counter - has counter which totalises comparison of bits into flip-flops and second counter to provide gating - Google Patents
Check word compared with data using bit counter - has counter which totalises comparison of bits into flip-flops and second counter to provide gatingInfo
- Publication number
- FR2290709A1 FR2290709A1 FR7533790A FR7533790A FR2290709A1 FR 2290709 A1 FR2290709 A1 FR 2290709A1 FR 7533790 A FR7533790 A FR 7533790A FR 7533790 A FR7533790 A FR 7533790A FR 2290709 A1 FR2290709 A1 FR 2290709A1
- Authority
- FR
- France
- Prior art keywords
- counter
- flops
- flip
- bits
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
The input memory (11) in response to a read-out signal transmits data to the input of a gating circuit (13, 14, 19) coupled to the output memory (12). A check word based upon groups of 2, 4 or 8 bits may be used and the data examined for coincidence. The memory output is transmitted to AND gates (151 to 15n) coupled to an equal number of flip-flops (BF1 to BFn). A counter (20) records the number of 11 states in the specified locations against the groupings assigned in the check count. The read instruction steps a second counter (27) to provide inputs to a gating array (171 to 17n) to allow checked information to be entered in the output memory.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP49127321A JPS5152708A (en) | 1974-11-05 | 1974-11-05 | |
JP13164274A JPS5322414B2 (en) | 1974-11-15 | 1974-11-15 | |
JP49144709A JPS5171002A (en) | 1974-12-17 | 1974-12-17 | |
JP49146843A JPS5173347A (en) | 1974-12-23 | 1974-12-23 | Heiretsujohono chetsukuhoshiki |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2290709A1 true FR2290709A1 (en) | 1976-06-04 |
Family
ID=27471292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7533790A Withdrawn FR2290709A1 (en) | 1974-11-05 | 1975-11-05 | Check word compared with data using bit counter - has counter which totalises comparison of bits into flip-flops and second counter to provide gating |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE2549676A1 (en) |
FR (1) | FR2290709A1 (en) |
-
1975
- 1975-11-05 DE DE19752549676 patent/DE2549676A1/en active Pending
- 1975-11-05 FR FR7533790A patent/FR2290709A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
DE2549676A1 (en) | 1976-05-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |