SU475624A1 - Error Detection Device - Google Patents

Error Detection Device

Info

Publication number
SU475624A1
SU475624A1 SU885621A SU885621A SU475624A1 SU 475624 A1 SU475624 A1 SU 475624A1 SU 885621 A SU885621 A SU 885621A SU 885621 A SU885621 A SU 885621A SU 475624 A1 SU475624 A1 SU 475624A1
Authority
SU
USSR - Soviet Union
Prior art keywords
detection device
error detection
winding
cell
windings
Prior art date
Application number
SU885621A
Other languages
Russian (ru)
Inventor
Владимир Борисович Мараховский
Галина Ивановна Мендерская
Евгений Александрович Каневский
Original Assignee
Математический Институт Им.В.А.Стеклова
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Математический Институт Им.В.А.Стеклова filed Critical Математический Институт Им.В.А.Стеклова
Priority to SU885621A priority Critical patent/SU475624A1/en
Application granted granted Critical
Publication of SU475624A1 publication Critical patent/SU475624A1/en

Links

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Description

Предмет изобретени Subject invention

Устройство обнаружени  ошибок в разр де с избыточным кодированием, выполненное по способу вы влени  ошибочных комбинаций, отличаюшеес  тем, что, с целью обнаружени  ошибочных комбинаций двоично-дес тичного кода с избытком 3, оно выполнено на п ти ферротранзисторных  чейках, четыре из которых образуют попарным объединениемAn error detection device in a discharge with redundant coding, performed by a method of detecting erroneous combinations, characterized in that, in order to detect erroneous combinations of binary-decimal code with an excess of 3, it is performed on five ferrotransistor cells, four of which are paired by association

два устройства совпадени , п та  используетс  как элемент пам ти; входы старших разр дов соединены с обмотками записи первой схемы совпадени , вход первого разр да соедипен с обмоткой записи п той  чейки, вход второго разр да соединен с обмоткой списывани  п той  чейки, причем обмотка опроса размешепа на всех, кроме первой,  чейках, а выходные обмотки устройств совпадени  объединены .two matching devices, nth is used as a memory element; higher bit inputs are connected to the windings of the first coincidence circuit recording, the first bit input is connected to the fifth cell record winding, the second bit input is connected to the fifth cell write off winding, and the stirring winding is placed on all but the first cell, and the weekend the windings of the matching devices are combined.

/г sfi/ g sfi

«"

SU885621A 1964-02-26 1964-02-26 Error Detection Device SU475624A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU885621A SU475624A1 (en) 1964-02-26 1964-02-26 Error Detection Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU885621A SU475624A1 (en) 1964-02-26 1964-02-26 Error Detection Device

Publications (1)

Publication Number Publication Date
SU475624A1 true SU475624A1 (en) 1975-06-30

Family

ID=20437843

Family Applications (1)

Application Number Title Priority Date Filing Date
SU885621A SU475624A1 (en) 1964-02-26 1964-02-26 Error Detection Device

Country Status (1)

Country Link
SU (1) SU475624A1 (en)

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